Customized generation and secure authenticated processing of transfer instrument
US-12586051-B1 · Mar 24, 2026 · US
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Duane Michael patents
Duane Michael is listed as an inventor on 24 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Duane Michael |
| Total patents | 24 |
| First publication | May 26, 2015 |
| Latest publication | Mar 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Automated event tracking and conditional asset transfer
US-12572905-B1 · Mar 10, 2026 · US
Optimization of data presentation
US-12567084-B1 · Mar 3, 2026 · US
Peer-to-Peer Data Object Transfer and State Management
US-2025363480-A1 · Nov 27, 2025 · US
Peer-to-peer data object transfer and state management
US-12293351-B2 · May 6, 2025 · US
Rewards for a virtual cash card
US-2024119449-A1 · Apr 11, 2024 · US
Rewards for a virtual cash card
US-11842345-B2 · Dec 12, 2023 · US
Peer-to-Peer Data Object Transfer and State Management
US-2023045946-A1 · Feb 16, 2023 · US
Cryptocurrency rewards for a virtual cash card
US-11526882-B2 · Dec 13, 2022 · US
Cryptocurrency rewards for a virtual cash card
US-2022172200-A1 · Jun 2, 2022 · US
Recent patents
Latest publications not already listed above.
Cryptocurrency rewards for a virtual cash card
US-2022172194-A1 · Jun 2, 2022 · US
Semiconductor structure with multiple transistors having various threshold voltages
US-10217838-B2 · Feb 26, 2019 · US
Semiconductor Structure With Multiple Transistors Having Various Threshold Voltages and Method of Fabrication Thereto
US-2018261683-A1 · Sep 13, 2018 · US
Semiconductor structure with multiple transistors having various threshold voltages
US-10014387-B2 · Jul 3, 2018 · US
Semiconductor structure with multiple transistors having various threshold voltages
US-9812550-B2 · Nov 7, 2017 · US
Semiconductor Structure with Multiple Transistors Having Various Threshold Voltages
US-2017141209-A1 · May 18, 2017 · US
CMOS Structures and Processes Based on Selective Thinning
US-2016307907-A1 · Oct 20, 2016 · US
CMOS structures and processes based on selective thinning
US-9391076-B1 · Jul 12, 2016 · US
Method for fabricating a transistor with reduced junction leakage current
US-9368624-B2 · Jun 14, 2016 · US
Semiconductor Structure with Multiple Transistors Having Various Threshold Voltages
US-2016163823-A1 · Jun 9, 2016 · US
Semiconductor structure with multiple transistors having various threshold voltages
US-9299698-B2 · Mar 29, 2016 · US
High uniformity screen and epitaxial layers for CMOS devices
US-9196727-B2 · Nov 24, 2015 · US
High Uniformity Screen and Epitaxial Layers for CMOS Devices
US-2015333144-A1 · Nov 19, 2015 · US
Deeply depleted MOS transistors having a screening layer and methods thereof
US-9041126-B2 · May 26, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Mie Fujitsu Semiconductor Ltd | 13 |
| Block Inc | 9 |
| Square Inc | 3 |
| Suvolta Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 12 |
| H10D62/371 | 11 |
| H10D30/601 | 11 |
| H10D62/314 | 10 |
| G06Q20/065 | 9 |