Threshold voltage and well implantation method for semiconductor devices

Patent metadata

Field	Value
Publication number	US-9780002-B1
Application number	US-201615173766-A
Country	US
Kind code	B1
Filing date	Jun 6, 2016
Priority date	Jun 6, 2016
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

Methodologies for patterning and implantation are provided Embodiments include forming fins; forming an SiN over the fins; forming an a-Si layer over the SiN; forming and patterning a first patterning layer over the a-Si layer; etching through the a-Si layer using the first patterning layer as a mask; removing the first patterning layer; implanting ions in exposed groups of fins; forming and patterning a second patterning layer to expose a first group of fins and a portion of the a-Si layer on opposite sides of the first group of fins; implanting ions in a first region of the first group of fins; forming a third patterning layer over the first region of the first group of fins and exposing a second region of the first group of fins; and implanting ions in the second region of the first group of fins.

First claim

What is claimed is:

1. A method comprising:
forming groups of fins in regions over a substrate;
forming an silicon nitride (SiN) over the groups of fins;
forming an amorphous silicon (a-Si) layer over the SiN;
forming and patterning a first patterning layer over the a-Si layer;
etching through the a-Si layer down to the SiN using the first patterning layer as a mask;
removing the first patterning layer;
implanting ions in exposed groups of fins following the etching of the a-Si layer;
forming and patterning a second patterning layer to expose a first group of fins and a portion of the a-Si layer on opposite sides of the first group of fins;
implanting ions in a first region of the first group of fins;
forming a third patterning layer over the first region of the first group of fins and exposing a second region of the first group of fins; and
implanting ions in the second region of the first group of fins.

2. The method according to claim 1 , further comprising:
forming an oxide layer between individual fins and between the groups of fins and forming the SiN over the oxide layer.

3. The method according to claim 2 , further comprising:
forming a fourth patterning layer over at least the second region of the first group of fins.

4. The method according to claim 3 , further comprising:
removing the fourth patterning layer to expose a third region of the first group of fins.

5. The method according to claim 4 , further comprising:
implanting ions in the third region of the first group of fins.

6. The method according to claim 5 , further comprising:
depositing a second oxide layer over the SiN and a-Si layer.

7. The method according to claim 6 , further comprising:
planarizing the second oxide layer down to an upper surface of the a-Si layer.

8. The method according to claim 7 , further comprising:
removing the a-Si layer after planarizing the second oxide layer.

9. The method according to claim 8 , further comprising:
implanting ions in exposed second groups of fins following the removal of the a-Si layer.

10. The method according to claim 8 , further comprising:
forming and patterning a fifth patterning layer to expose the second group of fins and a portion of the second oxide layer on opposite sides of the second group of fins.

11. The method according to claim 10 , further comprising:
implanting ions in a first region of the second group of fins.

12. The method according to claim 11 , further comprising:
forming a sixth patterning layer over the first region of the second group of fins and exposing a second region of the second group of fins.

13. The method according to claim 12 , further comprising:
implanting ions in the second region of the second group of fins.

14. The method according to claim 13 , further comprising:
forming a seventh patterning layer over the second region of the second group of fins and exposing a third region of the second group of fins.

15. The method according to claim 14 , further comprising:
removing the seventh patterning layer;
removing the second oxide layer; and
removing the SiN.

16. A method comprising:
forming groups of fins in regions over a substrate;
forming a silicon nitride (SiN) over the groups of fins;
forming an amorphous silicon (a-Si) over the SiN;
forming and patterning a first patterning layer over the a-Si layer;
etching through the a-Si layer down to the SiN using the first patterning layer as a mask;
removing the first patterning layer;
implanting ions in exposed groups of fins following the etching of the a-Si layer;
forming and patterning a second patterning layer to expose a first group of fins in an NFET region and a portion of the a-Si layer formed over a second group of fins in a PFET region;
implanting ions in a first region of the first group of fins;
forming a third patterning layer over at least the first region of the first group of fins and exposing a second region of the first group of fins; and
implanting ions in the second region of the first group of fins.

17. The method according to claim 16 , further comprising:
forming a fourth patterning layer over at least the second region of the first group of fins and exposing a third region of the first group of fins; and
implanting ions in the third region of the first group of fins.

18. The method according to claim 17 , further comprising:
depositing an oxide layer over the SiN and a-Si layer;
planarizing the oxide layer down to an upper surface of the a-Si layer;
removing the a-Si layer; and
implanting ions in groups of fins exposed following the removal of the a-Si layer.

19. The method according to claim 18 , further comprising:
forming and patterning a fifth patterning layer to expose the second group of fins in the PFET region and a portion of the oxide layer in a second NFET region;
implanting ions in a first region of the second group of fins;
forming a sixth patterning layer over at least the first region of the second group of fins and exposing a second region of the second group of fins;
implanting ions in the second region of the second group of fins;
forming a seventh patterning layer over at least the second region of the second group of fins and exposing a third region of the second group of fins;
removing the seventh a-Si layer;
removing the oxide layer; and
removing the SiN.

20. A method comprising:
forming groups of fins in regions over a substrate, wherein an oxide layer is formed between individual fins and between the groups of fins;
forming a silicon nitride (SiN) over the oxide layer;
forming an amorphous silicon (a-Si) layer over the SiN;
forming and patterning a first patterning layer over the a-Si layer;
etching through the a-Si layer down to the SiN using the first patterning layer as a mask;
removing the first patterning layer;
implanting ions in exposed groups of fins following the etching of the a-Si layer;
forming and patterning a second patterning layer to expose a first group of fins in an NFET region and a portion of the a-Si layer formed over a second group of fins in a PFET region;
implanting ions in a first region of the first group of fins;
forming a third patterning layer over at least the first region of the first group of fins and exposing a second region of the first group of fins;
implanting ions in the second region of the group of fins;
forming a fourth patterning layer over at least the second region of the first group of fins;
removing the fourth patterning layer to expose a third region of the first group of fins; and
implanting ions in the third region of the third group of fins.

Assignees

• Globalfoundries Inc

Inventors

• Dai Xintuo
• Greene Brian
• Kumar Mahender
• Dechene Daniel J
• Jaeger Daniel

Classifications

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10P76/20

  of masks comprising organic materials · CPC title

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title