Methods of forming fin isolation regions on FinFET semiconductor devices by implantation of an oxidation-retarding material

Patent metadata

Field	Value
Publication number	US-9673083-B2
Application number	US-201514608729-A
Country	US
Kind code	B2
Filing date	Jan 29, 2015
Priority date	Jan 29, 2015
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, the fin having a lower first section that contains an oxidation-retarding implant region and an upper second section that is substantially free of the oxidation-retarding implant region, forming a sidewall spacer on opposite sides of the upper portion of the fin, forming a first layer of insulating material adjacent the sidewall spacers and the upper second section of the lower portion of the fin, and, with the first layer of insulating material in position, performing a thermal anneal process to convert the portion of the upper second section of the fin that is in contact with the first layer of insulating material into an oxide fin isolation region positioned under the fin above the lower first section of the fin.

First claim

What is claimed:

1. A method, comprising:
forming a fin in a semiconductor substrate, said fin comprising a lower portion and an upper portion, wherein said lower portion of said fin has tapered sidewalls and is comprised of a lower first section containing an oxidation-retarding implant region and an upper second section that is substantially free of said oxidation-retarding implant region;
forming a sidewall spacer on opposite sides of said upper portion of said fin, wherein said sidewall spacers cover said upper portion of said fin but do not cover said upper second section of said lower portion of said fin;
forming a first layer of insulating material adjacent said sidewall spacers and said upper second section of said lower portion of said fin; and
with said first layer of insulating material in position, performing a thermal anneal process to convert the portion of said upper second section of said fin that is in contact with said first layer of insulating material into an oxide fin isolation region positioned under said fin above said lower first section of said fin.

2. The method of claim 1 , wherein said forming said fin in said semiconductor substrate, comprises:
forming said fin in said substrate and thereafter forming said sidewalls spacers adjacent said upper portion of said fin; and
after forming said fin and said sidewall spacers, performing an ion implantation process to form said oxidation-retarding implant region in said lower first section of said lower portion of said fin.

3. The method of claim 2 , wherein said first layer of insulating material is formed after said fin and said sidewall spacers are formed and after said ion implantation process is performed.

4. The method of claim 1 , wherein said forming said fin in said semiconductor substrate, comprises:
forming said fin in said substrate and thereafter forming said sidewall spacers adjacent said upper portion of said fin;
after forming said fin and said sidewall spacers, forming said first layer of insulating material; and
after forming said fin, said sidewall spacers and said first layer of insulating material, performing an ion implantation process to form said oxidation-retarding implant region in said lower first section of said lower portion of said fin.

5. The method of claim 1 , wherein said forming said fin in said semiconductor substrate, comprises:
forming a hard mask material layer above an upper surface of said substrate;
performing an ion implantation process through said hard mask material layer so as to form said oxidation-retarding implant region in said substrate;
patterning said hard mask material layer so as to define a patterned hard mask; and
performing an etching process through said patterned hard mask to form a plurality of fin-formation trenches that define said fin, wherein said lower portion of said fin is comprised of said lower first section containing said oxidation-retarding implant region and said upper second section that is substantially free of said oxidation-retarding implant region.

6. The method of claim 1 , wherein said performing said thermal anneal process comprises performing an anneal process at a temperature that falls within a range of about 400-1300° C. in an oxidation ambient.

7. The method of claim 1 , wherein said first layer of insulating material is comprised of silicon dioxide.

8. The method of claim 1 , wherein said oxidation-retarding implant region is formed by performing an ion implantation process using one of nitrogen, argon and xenon.

9. The method of claim 1 , wherein said ion implantation process is performed using an implant dose of about 1E13-1E15 ions/cm 2 and an implant energy of about 30-100 keV.

10. A method, comprising:
forming a plurality of fin-formation trenches in a semiconductor substrate so as to define a fin comprised of a lower portion and an upper portion, wherein said lower portion of said fin has tapered sidewalls;
forming a sidewall spacer on opposite sides of said upper portion of said fin;
after forming said fin and said sidewall spacers, performing an ion implantation process to form an oxidation-retarding implant region in a lower first section of said lower portion of said fin while leaving an upper second section of said fin that is not covered by said sidewall spacers substantially free of said oxidation-retarding implant region;
forming a first layer of insulating material adjacent said sidewall spacers and said upper second section of said lower portion of said fin; and
with said first layer of insulating material in position, performing a thermal anneal process to convert the portion of said upper second section of said fin that is in contact with said first layer of insulating material into an oxide fin isolation region positioned under said fin above said lower first section of said fin.

11. The method of claim 10 , wherein said performing said thermal anneal process comprises performing an anneal process at a temperature that falls within a range of about 400-1300° C. in an oxidation ambient.

12. The method of claim 10 , wherein said first layer of insulating material is comprised of silicon dioxide.

13. The method of claim 10 , wherein said oxidation-retarding implant region is formed by performing an ion implantation process using one of nitrogen, argon and xenon.

14. The method of claim 10 , wherein said ion implantation process is performed using an implant dose of about 1E13-1E15 ions/cm 2 and an implant energy of about 30-100 keV.

15. A method, comprising:
forming a plurality of fin-formation trenches in a semiconductor substrate so as to define a fin comprised of a lower portion and an upper portion, wherein said lower portion of said fin has tapered sidewalls;
forming a sidewall spacer on opposite sides of said upper portion of said fin;
forming a first layer of insulating material in said trenches adjacent said sidewall spacers, said lower portion of said fin and said upper portion of said fin;
after forming said fin, said sidewall spacers and said first layer of insulating material, performing an ion implantation process to form an oxidation-retarding implant region in a lower first section of said lower portion of said fin with said first layer of insulating material in position; and
performing a thermal anneal process to convert the portion of said upper second section of said fin that is in contact with said first layer of insulating material into an oxide fin isolation region positioned under said fin above said lower first section of said fin.

16. The method of claim 15 , wherein said performing said thermal anneal process comprises performing an anneal process at a temperature that falls within a range of about 400-1300° C. in an oxidation ambient.

17. The method of claim 15 , wherein said first layer of insulating material is comprised of silicon dioxide.

18. The method of claim 15 , wherein said oxidation-retarding implant region is formed by performing an ion implantation process using one of nitrogen, argon and xenon.

19. The method of claim 15 , wherein said ion implantation process is performed using an implant dose of about 1E13-1E15 ions/cm 2 and an implant energy of about 30-100 keV.

20. A method, comprising:
forming a hard mask material layer above an upper surface of a semiconductor substrate;
performing an ion implantation process through said hard mask material layer so as to form an oxidation-retarding implant region in said substrate;
patterning said hard mask material layer so as to define

Assignees

• Globalfoundries Inc
• IBM

Inventors

• Jacob Ajey Poovannummoottil
• Doris Bruce
• Cheng Kangguo
• Khakifirooz Ali
• Rim Kern

Classifications

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P14/6309

  of silicon in uncombined form, i.e. pure silicon · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title