Block patterning process for post fin

Patent metadata

Field	Value
Publication number	US-9312191-B2
Application number	US-201414459407-A
Country	US
Kind code	B2
Filing date	Aug 14, 2014
Priority date	Aug 14, 2014
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A method of reducing etch time needed for patterning an organic planarization layer (OPL) in a block mask stack so as to minimize damages to gate structures and fin structures in a block mask patterning process is provided. The block mask stack including an OPL, a developable antireflective coating (DARC) layer atop the OPL and a photoresist layer atop the DARC layer is employed to mask one conductivity type of FinFET while exposing the other conductivity type FinFET during source/drain ion implantation. The OPL is configured to have a minimum thickness sufficient to fill in spaces between semiconductor fins and to cover the semiconductor fins. The DARC layer is configured to planarize topography of semiconductor fins so as to provide a planar top surface for the ensuing lithography and etch processes.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
forming a plurality of semiconductor fins on a substrate comprising a buried insulator layer over a handle substrate;
forming a gate structure over a portion of each of the plurality of semiconductor fins;
forming a contact trench in the substrate, wherein the contact trench extends through the buried insulator layer and into the handle substrate;
forming an organic planarization layer (OPL) over the substrate, wherein the OPL is deposited to a minimum thickness sufficient to fill in spaces between the plurality of semiconductor fins and to cover the plurality of semiconductor fins, and the OPL fills in the contact trench, and wherein a top surface of the OPL is non-planar;
forming a developable antireflective coating (DARC) layer on the top surface of the OPL, wherein the DARC layer provides a substantially planar top surface;
forming a photoresist layer on the top surface of the DARC layer;
exposing a portion of the photoresist layer to a radiation, the radiation creating a pattern in exposed portion of the photoresist layer and a portion of the DARC layer underlying the exposed portion of the photoresist layer;
removing the exposed portion of the photoresist layer and the portion of the DARC layer underlying the exposed portion of the photoresist layer to expose a portion of the OPL; and
removing exposed portion of the OPL to form an opening, wherein the opening exposes a first set of the plurality of semiconductor fins and leaves a second set of the plurality of semiconductor fins covered.

2. The method of claim 1 , wherein the plurality of semiconductor fins have a height ranging from 10 nm to 50 nm.

3. The method of claim 1 , wherein the OPL comprises polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylenether resin, or polyphenylene sulfide resin.

4. The method of claim 3 , wherein the OPL has a thickness ranging from 40 nm to 60 nm.

5. The method of claim 1 , wherein the DARC layer comprises a polymer containing carboxylic acid moieties with different crosslinker, photoacid generator, quencher, and solvents.

6. The method of claim 5 , wherein the DARC layer has a thickness ranging from 20 nm to 60 nm.

7. The method of claim 1 , wherein the photoresist layer comprises polyacrylate or polyhydroxystyrene.

8. The method of claim 1 , wherein the removing the exposed portion of the photoresist layer and the portion of the DARC layer underlying the exposed portion of the photoresist layer is accomplished by a developer.

9. The method of claim 8 , wherein the developer is an aqueous alkaline solution.

10. The method of claim 1 , wherein the removing the exposed portion of the OPL is accomplished by reactive ion etching.

11. The method of claim 10 , wherein the reactive ion etching of the OPL removes the OPL completely from the contact trench.

12. The method of claim 11 , further comprising filling the contact trench with an electrically conductive material to provide a body contact.

13. The method of claim 12 , wherein the electrically conductive material comprises doped polysilicon or a metal comprising tungsten.

14. The method of claim 1 , further comprising implanting a first type dopant into portions of the exposed portions of the first set of the plurality of semiconductor fins on opposite sides of the gate structure to form source and drain regions in the first set of the plurality of semiconductor fins.

15. The method of claim 14 , wherein the first set of the plurality of semiconductor fins comprises p-type semiconductor fins and the second set of the plurality of semiconductor fins comprises n-type semiconductor fins, and wherein the first type of dopant is an n-type dopant.

16. The method of claim 1 , wherein the gate structure comprises a gate dielectric, a gate conductor and a dielectric cap.

17. The method of claim 1 , further comprising forming a gate spacer on sidewalls of the gate structure.

Assignees

• Globalfoundries Inc

Inventors

• Li Wai-Kin

Classifications

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10P76/20

  of masks comprising organic materials · CPC title

• H10P50/287

  by chemical means · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title