Forksheet transistor multilayer bottom isolation region
US-2026090038-A1 · Mar 26, 2026 · US
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Kumar Mahender patents
Kumar Mahender is listed as an inventor on 19 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Kumar Mahender |
| Total patents | 19 |
| First publication | Oct 3, 2017 |
| Latest publication | Mar 26, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Backside local well tap
US-2026040636-A1 · Feb 5, 2026 · US
Semiconductor device with a junction in backside power delivery network
US-2026018455-A1 · Jan 15, 2026 · US
Insulating plug in backside power delivery network
US-2026013222-A1 · Jan 8, 2026 · US
Via-to-backside power rail structure
US-2025318238-A1 · Oct 9, 2025 · US
Enhanced power rail connection
US-2025285975-A1 · Sep 11, 2025 · US
Parallel lines formed by isolation cut
US-2025259940-A1 · Aug 14, 2025 · US
Semiconductor backside contact spacer engineering
US-2025261424-A1 · Aug 14, 2025 · US
Robust backside contact formation
US-2025254915-A1 · Aug 7, 2025 · US
Contact and placeholder configuration for backside power delivery devices
US-2025203933-A1 · Jun 19, 2025 · US
Recent patents
Latest publications not already listed above.
Irregular-shaped power rail in cell power distribution
US-2024321748-A1 · Sep 26, 2024 · US
Transistor with recessed cross couple for gate contact over active region integration
US-10770388-B2 · Sep 8, 2020 · US
Integrated circuit products with gate structures positioned above elevated isolation structures
US-10566328-B2 · Feb 18, 2020 · US
Transistor with recessed cross couple for gate contact over active region integration
US-2019385946-A1 · Dec 19, 2019 · US
Methods of forming vertical field effect transistors with self-aligned contacts and the resulting structures
US-10461186-B1 · Oct 29, 2019 · US
Methods of forming gate structures above elevated isolation structures
US-2019267371-A1 · Aug 29, 2019 · US
Self-aligned gate isolation
US-2019139830-A1 · May 9, 2019 · US
Methods to control fin tip placement
US-9812324-B1 · Nov 7, 2017 · US
Threshold voltage and well implantation method for semiconductor devices
US-9780002-B1 · Oct 3, 2017 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 13 |
| Globalfoundries Inc | 6 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 12 |
| H10D64/017 | 10 |
| H10D84/0158 | 7 |
| H10D84/0149 | 7 |
| H10D84/834 | 6 |