Delta-Sigma ADC with wait-for-sync feature

Patent metadata

Field	Value
Publication number	US-9692446-B2
Application number	US-201615281354-A
Country	US
Kind code	B2
Filing date	Sep 30, 2016
Priority date	Nov 11, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

An integrated circuit (IC) chip containing a Delta-Sigma (ΔΣ) filter module for a ΔΣ analog-to-digital converter and a method of providing analog to digital conversion are disclosed. The IC chip includes a ΔΣ filter that is connected to receive a digital data stream created by a ΔΣ modulator, provide a multibit data value when a counter reaches a selected number of received bits, and reset the counter responsive to receiving a synchronization pulse. The IC chip also includes a FIFO buffer connected to store the multibit data value only when a synchronization flag is on and to send an interrupt towards a processing unit only after storing a selected number of multibit data values. The IC chip further includes a synchronization module connected to turn on the synchronization flag responsive to receiving the synchronization pulse and to turn off the synchronization flag responsive to the sending of the interrupt.

First claim

What is claimed is:

1. An integrated circuit (IC) chip containing a Delta-Sigma filter module (DSFM) for a Delta-Sigma analog-to-digital converter, said DSFM comprising:
a Delta-Sigma filter connected to receive a digital data stream created by a Delta-Sigma modulator, provide a multibit data value when a counter reaches a selected number of received bits, and reset said counter responsive to receiving a synchronization pulse;
a first-in, first-out (FIFO) buffer connected to store said multibit data value only when a synchronization flag is on and to send an interrupt towards a processing unit only after storing a selected number of said multibit data values; and
a synchronization module connected to turn on said synchronization flag responsive to receiving said synchronization pulse and to turn off said synchronization flag responsive to the sending of said interrupt.

2. The IC chip as recited in claim 1 wherein said FIFO buffer is connected, responsive to sending said interrupt, to provide said multibit data values stored in said FIFO to the processing unit.

3. The IC chip as recited in claim 2 wherein said FIFO buffer is further connected to be cleared after providing said multibit outputs to said processing unit.

4. The IC chip as recited in claim 3 wherein said synchronization pulse is synchronized to a control signal.

5. The IC chip as recited in claim 4 wherein said control signal is related to a pulse width modulation signal.

6. The IC chip as recited in claim 5 wherein said selected number is configurable.

7. A method of providing analog to digital (ADC) conversion comprising:
receiving, at a Delta-Sigma (ΔΣ) filter for a ΔΣ analog-to-digital (ADC) converter, a stream of digital data from a ΔΣ modulator and providing a multibit data value and a data-ready signal when a counter reaches a given value;
storing said multibit data value in a first-in first-out (FIFO) buffer only if a synchronization flag is turned on;
responsive to receiving a synchronization pulse at said ΔΣ filter, resetting said counter to zero, and turning on said synchronization flag; and
responsive to storing a selected number of multibit data values in said FIFO buffer, sending an interrupt towards a processing unit and turning off said synchronization flag.

8. The method of providing ADC conversion as recited in claim 7 further comprising responsive to sending said interrupt towards said processing unit, providing said multibit data values in said FIFO buffer to said processing unit.

9. The method of providing ADC conversion as recited in claim 8 further comprising clearing said FIFO buffer after providing said multibit data values to said processing unit.

10. The method of providing analog to digital conversion results as recited in claim 9 wherein said synchronization pulses are synchronized to a control signal.

11. The method of providing ADC conversion as recited in claim 10 wherein said control signal is a pulse width modulation signal.

Assignees

• Texas Instruments Inc

Inventors

• Landers Robert James

Classifications

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• H03M3/462 Primary

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• H03M3/324

  characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement · CPC title