Apparatus and method for providing interface between modem and RF chip

Patent metadata

Field	Value
Publication number	US-9362945-B2
Application number	US-201213705529-A
Country	US
Kind code	B2
Filing date	Dec 5, 2012
Priority date	Dec 6, 2011
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

An Analog-Digital Converter (ADC) is provided. The ADC includes a plurality of sigma-delta modulators, a plurality of decimators, a plurality of differentiators, and a plurality of XOR operators. The plurality of sigma-delta modulators respectively convert analog signals to digital pulses. The plurality of decimators respectively convert a first sampling rate of a corresponding digital pulse to a second sampling rate which is lower than the first sampling. The plurality of differentiators respectively differentiate signals converted at the second sampling rate to perform delta modulation. The plurality of XOR operators extract a signal component changing with respect to the delta-modulated signals. Therefore, the number of interface pins between a modem and an RFIC can be reduced.

First claim

What is claimed is:

1. An Analog-Digital Converter (ADC), the ADC comprising:
a plurality of sigma-delta modulators for respectively converting analog signals to digital pulses;
a plurality of decimators for respectively converting a first sampling rate of a corresponding digital pulse to a second sampling rate which is lower than the first sampling rate;
a plurality of differentiators for respectively differentiating signals converted at the second sampling rate to perform delta modulation; and
a plurality of XOR operators for respectively extracting a changing signal component with respect to the delta-modulated signals.

2. The ADC of claim 1 , further comprising:
an encoder for reducing a number of output bits by compressing output signals from the plurality of XOR operators.

3. The ADC of claim 2 , wherein the encoder uses an algorithm compressing the output signals from the plurality of XOR operators via a horizontal-vertical conversion structure.

4. The ADC of claim 1 , further comprising:
a multiplexer for performing multiplexing on output signals which are operatively output from the plurality of XOR operators.

5. The ADC of claim 1 , wherein the plurality of XOR operators respectively perform an XOR operation on a delta-modulated first signal, and a second signal following the first signal in time and delta-modulated after passing through the corresponding sigma-delta modulator, the corresponding decimator, and the corresponding differentiator.

6. The ADC of claim 1 , wherein the plurality of sigma-delta modulators respectively comprise:
an integrator for integrating a difference between an analog input signal and a fed-back 1 bit output of a Digital-Analog Converter (DAC);
a comparator for outputting “1” in a section where an output of the integrator is positive (+) and outputting “0” in a section where an output of the integrator is negative (−); and
a latch for synchronizing an output of the comparator with a clock.

7. The ADC of claim 1 , wherein a number of the plurality of sigma-delta modulators, the plurality of decimators, and the plurality of differentiators is determined by the number of Radio Frequency (RF) chains.

8. The ADC of claim 1 , wherein the plurality of XOR operators respectively extract a changing signal component with respect to the delta-modulated signals using an XOR operation.

9. A receiver comprising:
a baseband processor configured to:
convert a plurality of Radio Frequency (RF) chain signals to baseband signals by converting the plurality of RF chain signals to digital signals,
convert a high sampling rate of at least a portion of the digital signals to a low sampling rate using a decimator,
differentiate signals converted to the low sampling rate,
perform a delta conversion on the differentiated signals having the low sampling rate,
extract, using a plurality of XOR operators, a changing signal component with respect to the delta-modulated signals, and
compress the baseband signals based on a result of the plurality of XOR operators; and

an interface unit configured to transfer the compressed baseband signals to a modem,
wherein the modem demodulates the baseband signals.

10. The receiver of claim 9 , wherein the baseband processor comprises:
a plurality of Low Noise Amplifiers (LNAs) for amplifying a plurality of RF chain signals;
a plurality of mixers for down-converting the low-noise amplified RF chain signals;
a plurality of analog baseband units for respectively filtering and amplifying the down-converted RF chain signals; and
a plurality of Analog-to-Digital Converters (ADCs) for converting the amplified down-converted RF chain signals to digital signals.

11. The receiver of claim 10 , wherein the plurality of ADCs respectively comprise:
a plurality of sigma-delta modulators for respectively converting analog signals to digital pulses;
a plurality of decimators for respectively converting a first sampling rate of a corresponding digital pulse to a second sampling rate which is lower than the first sampling rate;
a plurality of differentiators for respectively differentiating signals converted at the second sampling rate to perform delta modulation; and
a plurality of XOR operators for performing an XOR operation on the delta-modulated signals.

12. The receiver of claim 11 , further comprising:
an encoder for reducing a number of output bits by compressing XOR-operated signals.

13. The receiver of claim 12 , wherein the encoder uses an algorithm compressing the XOR-operated signals via a horizontal-vertical conversion structure.

14. The receiver of claim 11 , further comprising:
a multiplexer for performing multiplexing on XOR-operated signals to reduce the number of output bits.

15. An analog-digital converting method, the method comprising:
respectively converting analog signals to digital pulses;
respectively converting a first sampling rate of a corresponding digital pulse to a second sampling rate which is lower than the first sampling rate;
respectively differentiating signals converted at the second sampling rate to perform delta modulation; and
respectively performing an XOR operation on the delta-modulated signals.

16. The method of claim 15 , further comprising:
reducing a number of output bits by compressing XOR-operated signals.

17. The method of claim 15 , further comprising:
using an algorithm compressing XOR-operated signals via a horizontal-vertical conversion structure.

18. The method of claim 15 , further comprising:
performing multiplexing on XOR-operated signals to reduce the number of output bits.

19. The method of claim 15 , wherein the performing of the XOR operation on the delta-modulated signals comprises:
performing the XOR operation on a delta-modulated first signal, and a second signal following the first signal in time and delta-modulated via the first operation to third operation.

20. The method of claim 15 , wherein the converting of the analog signals to the digital pulses, respectively, comprises:
integrating a difference between an analog input signal and a fed-back 1 bit output of a Digital-Analog Converter (DAC);
outputting “1” in a section where an output of the integration result is positive (+) and outputting “0” in a section where an output of the integration result is negative (−); and
synchronizing the output with a clock.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jong-Woo

Classifications

• H04B1/18 Primary

  Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H) · CPC title

• H03M3/462 Primary

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M7/3048

  Conversion to or from one-bit differential modulation only, e.g. delta modulation [DM] (H03M7/3004 takes precedence) · CPC title

• H03M3/466

  Multiplexed conversion systems · CPC title

• H04L27/06

  Demodulator circuits; Receiver circuits · CPC title