Readout circuit and method of using the same

Patent metadata

Field	Value
Publication number	US-9706143-B2
Application number	US-201514947554-A
Country	US
Kind code	B2
Filing date	Nov 20, 2015
Priority date	May 14, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A readout circuit includes a first analog circuit configured to receive an output of a first sub-array of a pixel array and to output a first signal based on the received output of the first sub-array. A second analog circuit is configured to receive an output of a second sub-array of the pixel array and to output a second signal based on the received output of the second sub-array. A first digital circuit is configured to receive the first signal and convert the first signal to a first digital signal, and receive the second signal and convert the second signal to a second digital signal.

First claim

What is claimed is:

1. A readout circuit comprising:
a first analog circuit configured to receive an output of a first sub-array of a pixel array and to output a first signal based on the received output of the first sub-array;
a second analog circuit configured to receive an output of a second sub-array of the pixel array and to output a second signal based on the received output of the second sub-array; and
a first digital circuit configured to:
receive the first signal and convert the first signal to a first digital signal; and
receive the second signal and convert the second signal to a second digital signal.

2. The readout circuit of claim 1 , wherein at least one of the first analog circuit or the second analog circuit comprises a multiplying digital to analog converter (MDAC), a delta-sigma converter, a single slope analog to digital converter (ADC), a pipeline ADC, a dual slope ADC, a successive approximation register (SAR) ADC, or a cyclic ADC.

3. The readout circuit of claim 1 , wherein the first digital circuit comprises a digital memory.

4. The readout circuit of claim 3 , wherein the first digital circuit further comprises a decimation filter or an error correction circuit.

5. The readout circuit of claim 1 , further comprising:
a first line memory connected to the first analog circuit, wherein the first analog circuit is configured to receive the output of the first sub-array from the first line memory; and
a second line memory connected to the second analog circuit, wherein the second analog circuit is configured to receive the output of the second sub-array from the second line memory.

6. The readout circuit of claim 1 , further comprising:
a third analog circuit configured to receive an output of a third sub-array of the pixel array and to output a third signal based on the received output of the third sub-array;
a fourth analog circuit configured to receive an output of a fourth sub-array of the pixel array and to output a fourth signal based on the received output of the fourth sub-array;
a second digital circuit configured to:
receive the third signal and convert the third signal to a third digital signal; and
receive the fourth signal and convert the fourth signal to a fourth digital signal.

7. The readout circuit of claim 6 , further comprising a multiplexer configured to receive the first digital signal, the second digital signal, the third digital signal and the fourth digital signal and to output an output signal of the readout circuit.

8. The readout circuit of claim 7 , wherein
the first digital circuit has an operating frequency two times faster than an operating frequency of at least one of the first analog circuit or the second analog circuit, and
the multiplexer has an operating frequency two times faster than the operating frequency of the digital circuit.

9. The readout circuit of claim 1 , wherein the first digital circuit has an operating frequency two times faster than an operating frequency of at least one of the first analog circuit or the second analog circuit.

10. The readout circuit of claim 1 , further comprising:
a first vertical scanner configured to selectively activate a first pixel of the first sub-array; and
a second vertical scanner configured to selectively activate a second pixel of the second sub-array.

11. The readout circuit of claim 10 , wherein the first pixel of the first sub-array and the second pixel of the second sub-array are in a same column of the pixel array.

12. A three dimensional integrated circuit (3DIC) comprising:
a pixel array comprising a plurality of pixels arranged in a plurality of rows and a plurality of columns, the pixel array comprising a first sub-array and a second sub-array;
a first analog circuit configured to receive an output of the first sub-array and to generate a first signal based on the output of the first sub-array;
a second analog circuit configured to receive an output of the second sub-array and to generate a second signal based on the output of the second sub-array; and
a digital circuit configured to:
receive the first signal and generate a first digital signal based on the first signal; and
receive the second signal and generate a second digital signal based on the second signal.

13. The 3DIC of claim 12 , wherein the first analog circuit is on a different layer of the 3DIC from the pixel array.

14. The 3DIC of claim 12 , wherein the digital circuit is on a different layer of the 3DIC from the pixel array.

15. A method of operating a readout circuit, the method comprising:
receiving a first pixel signal from a first sub-array;
receiving a second pixel signal from a second sub-array;
generating a first signal based on the first pixel signal using a first analog circuit;
generating a second signal based on the second pixel signal using a second analog circuit different from the first analog circuit;
converting the first signal to a first digital signal using a digital circuit; and
converting the second signal to a second digital signal using the digital circuit.

16. The method of claim 15 , further comprising generating the first pixel signal on a first layer of a three dimensional integrated circuit (3DIC), wherein generating the first signal comprises generating the first signal on a second layer of the 3DIC different from the first layer.

17. The method of claim 15 , further comprising generating the first pixel signal on a first layer of a three dimensional integrated circuit (3DIC), wherein converting the first signal to a first digital signal comprises converting the first signal to a first digital signal on a second layer of the 3DIC different from the first layer.

18. The method of claim 15 , wherein at least one of generating the first signal or generating the second signal comprises utilizing a multiplying digital to analog converter (MDAC) or a delta-sigma converter.

19. The method of claim 15 , further comprising sequentially switching the digital circuit between the first analog circuit and the second analog circuit.

20. The method of claim 15 , further comprising:
activating a first pixel of the first sub-array with a first vertical scanner; and
activating a second pixel of the second sub-array with a second vertical scanner,
wherein the first sub-array and the second sub-array are sub-arrays of a pixel array and the first pixel and the second pixel are in a same column of the pixel array.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yamashita Yuichiro

Classifications

• H03M1/122 Primary

  Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages · CPC title

• H03M1/1205 Primary

  Multiplexed conversion systems · CPC title

• H04N25/00

  Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title

• H04N25/70

  SSIS architectures; Circuits associated therewith · CPC title

• H04N5/335

  Electricity · mapped topic