Analog-to-digital converter and an image sensor including the same

Patent metadata

Field	Value
Publication number	US-9473166-B2
Application number	US-201514692787-A
Country	US
Kind code	B2
Filing date	Apr 22, 2015
Priority date	Apr 23, 2014
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

An analog-to-digital converter includes a modulator, a controller, and a digital filter. The modulator generates a modulated signal based on an analog signal. The controller generates a weight control signal. The digital filter includes a weight signal generator and a first integrator. The weight signal generator generates a weight signal based on the weight control signal. The first integrator generates a digital signal corresponding to the analog signal by integrating the weight signal in response to the modulated signal. The weight control signal corresponds to a type and an order of the digital filter.

First claim

What is claimed is:

1. An analog-to-digital converter, comprising:
a modulator configured to generate a modulated signal based on an analog signal;
a controller configured to generate a weight control signal; and
a digital filter including a weight signal generator and a first integrator, the weight signal generator configured to generate a weight signal based on the weight control signal, the first integrator configured to generate a digital signal corresponding to the analog signal by integrating the weight signal in response to the modulated signal,
wherein the weight control signal corresponds to a type and an order of the digital filter.

2. The analog-to-digital converter of claim 1 , wherein the weight control signal includes a count control signal, a calculation control signal and a selection control signal.

3. The analog-to-digital converter of claim 2 , wherein the count control signal and the calculation control signal are periodic signals, respectively.

4. The analog-to-digital converter of claim 3 , wherein the weight signal generator initializes the weight signal at each of at least two periods of the count control signal and the calculation control signal in response to a reset signal generated by the controller,
wherein the first integrator initializes the digital signal at each of at least two periods of the count control signal and the calculation control signal in response to the reset signal.

5. The analog-to-digital converter of claim 2 , wherein the weight signal generator includes a counter, an integration unit, a first register, and a multiplexer,
wherein the counter generates a count signal by counting a number of edges of a clock signal in response to the count control signal,
wherein the integration unit generates an integrated signal by integrating the count signal in response to the calculation control signal,
wherein the multiplexer outputs one of the count signal, the integrated signal, and an output signal of the first register as the weight signal in response to the selection control signal.

6. The analog-to-digital converter of claim 5 , wherein the counter executes an up-counting for the count signal when the count control signal has logical value 1,
wherein the counter executes a down-counting for the count signal when the count control signal has logical value 0,
wherein the counter initializes the count signal in response to a reset signal generated by the controller.

7. The analog-to-digital converter of claim 5 , wherein the integration unit includes a calculation unit and a second register,
wherein the calculation unit generates a calculated signal by adding the integrated signal and the count signal or generates the calculated signal by subtracting the count signal from the integrated signal in response to the calculation control signal,
wherein the second register stores the calculated signal as the integrated signal in synchronization with the clock signal,
wherein the second register initializes the integrated signal in response to a reset signal generated by the controller.

8. The analog-to-digital converter of claim 7 , wherein the calculation unit generates the calculated signal by adding the integrated signal and the count signal when the calculation control signal has logical value 1,
wherein the calculation unit generates the calculated signal by subtracting the count signal from the integrated signal when the calculation control signal has logical value 0.

9. The analog-to-digital converter of claim 1 , wherein the first integrator includes a multiplexer and an integration unit,
wherein the multiplexer outputs one of the weight signal and logical value 0 as a multiplexer output signal in response to the modulated signal,
wherein the integration unit generates the digital signal by integrating the multiplexer output signal in response to a clock signal.

10. The analog-to-digital converter of claim 9 , wherein the integration unit includes an adder and a register,
wherein the adder generates an added signal by adding the multiplexer output signal and the digital signal,
wherein the register stores the added signal as the digital signal in synchronization with the clock signal,
wherein the register initializes the digital signal in response to a reset signal generated by the controller.

11. The analog-to-digital converter of claim 1 , wherein the first integrator includes a AND gate and an integration unit,
wherein the AND gate generates a register control signal by performing a logical AND operation on the modulated signal and a clock signal,
wherein the integration unit generates the digital signal by integrating the weight signal in response to the register control signal.

12. The analog-to-digital converter of claim 11 , wherein the integration unit includes an adder and a register,
wherein the adder generates an added signal by adding the weight signal and the digital signal,
wherein the register stores the added signal as the digital signal in synchronization with the register control signal,
wherein the register initializes the digital signal in response to a reset signal generated by the controller.

13. The analog-to-digital converter of claim 1 , wherein the type of the digital filter is a MATCHED type or a SINC type.

14. The analog-to-digital converter of claim 1 , wherein the type of the digital filter is a CUSTOM type having a user-defined frequency response.

15. The analog-to-digital converter of claim 1 , wherein the order of the digital filter is one, two or three.

16. An image sensor, comprising:
a pixel array including a plurality of pixels configured to output pixel signals corresponding to incident light;
a plurality of analog-to-digital converters configured to generate digital signals corresponding to the pixel signals; and
a switch circuit configured to select one of the digital signals based on a column selection signal, the switch circuit configured to output the selected digital signal, at least one of the plurality of the analog-to-digital converters including:
a modulator configured to generate a modulated signal based on the pixel signals;
a controller configured to generate a weight control signal; and
a digital filter including a weight signal generator and an integrator, the weight signal generator configured to generate a weight signal based on the weight control signal, the integrator configured to generate the digital signals corresponding to the pixel signals by integrating the weight signal in response to the modulated signal,

wherein the weight control signal corresponds to a type and an order of the digital filter.

17. An image sensor, comprising:
a pixel array including a plurality of pixels outputting first through (N)-th pixel signals corresponding to intensity of incident light (N is a natural number);
a controller configured to generate a weight control signal;
a weight signal generator configured to generate a weight signal based on the weight control signal;
first through (N)-th modulators;
first through (N)-th integrators; and
a switch circuit configured to select one of first through (N)-th digital signals based on a column selection signal, the switch circuit configured to output the selected digital signal,
wherein the weight control signal corresponds to a type and an order of digital filtering,
wherein the (K)-th modulator generates the (K)-th modulated signal based on the (K)-th pixel signal (K is a natural number less than or equal to N),
wherein the (K)-th integrator generates the (K)-th digital signal corresponding t

Assignees

• Samsung Electronics Co Ltd
• Industry-Academic Cooperation Foundation Yonsei Univ

Inventors

• Kim Jae-Hong
• Chae Youngcheol
• Song Seungwoo
• Jo Woojin
• Hwang Hyunseok

Classifications

• H03M3/466

  Multiplexed conversion systems · CPC title

• H03M3/344

  by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing · CPC title

• H03M1/123

  Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters · CPC title

• H04N25/78 Primary

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H03M1/0626

  by filtering · CPC title