Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016233231-A1
Application number	US-201514804768-A
Country	US
Kind code	A1
Filing date	Jul 21, 2015
Priority date	Feb 6, 2015
Publication date	Aug 11, 2016
Grant date	—

Abstract

A semiconductor device, including: interlayer insulating patterns and conductive patterns alternately stacked on a substrate; a channel structure passing through the interlayer insulating patterns and the conductive patterns; and tapered patterns interposed between the channel structure and the interlayer insulating patterns, spaced apart with any one of the conductive patterns interposed therebetween, and having widths decreased toward the substrate.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
interlayer insulating patterns and conductive patterns alternately stacked on a substrate; a channel structure passing through the interlayer insulating patterns and the conductive patterns; and tapered patterns interposed between the channel structure and the interlayer insulating patterns, spaced apart with any one of the conductive patterns interposed therebetween, and having widths decreased toward the substrate.

2 . The semiconductor device of claim 1 , wherein a width of an upper pattern among the tapered patterns is larger than a width of a lower pattern disposed to be closer to the substrate than the upper pattern.

3 . The semiconductor device of claim 1 , wherein the conductive patterns further protrude toward the channel structure than the interlayer insulating patterns.

4 . The semiconductor device of claim 1 , wherein a width of each of the interlayer insulating patterns is increased toward the substrate.

5 . The semiconductor device of claim 1 , wherein the tapered patterns include an oxide layer.

6 . The semiconductor device of claim 1 , wherein the interlayer insulating patterns are formed of a material having higher density than the tapered patterns.

7 . The semiconductor device of claim 1 , further comprising:
a memory layer formed to be in contact with an external wall of the channel structure to surround the channel structure.

8 . The semiconductor device of claim 1 , further comprising:
a memory layer configured to surround each of the conductive patterns.

9 . A semiconductor device, comprising:
lower interlayer insulating patterns and lower conductive patterns alternately stacked on a substrate; upper interlayer insulating patterns and upper conductive patterns alternately stacked on the lower interlayer insulating patterns and the lower conductive patterns; a channel structure including an upper region passing through the upper interlayer insulating patterns and the upper conductive patterns and a lower region passing through the lower interlayer insulating patterns and the lower conductive patterns; upper oxide layer patterns interposed between the upper region and the upper interlayer insulating patterns, spaced apart with any one of the upper conductive patterns interposed therebetween, and having widths decreased toward the substrate; and lower oxide layer patterns interposed between the lower region and the lower interlayer insulating patterns, and spaced apart with any one of the lower conductive patterns interposed therebetween.

10 . The semiconductor device of claim 9 , wherein a width of an upper pattern among the upper oxide layer patterns is larger than a width of a lower pattern disposed to be closer to the substrate than the upper pattern.

11 . The semiconductor device of claim 9 , wherein the upper conductive patterns and the lower conductive patterns further protrude toward the channel structure than the upper interlayer insulating patterns and the lower interlayer insulating patterns.

12 . The semiconductor device of claim 9 , wherein each of the upper oxide layer patterns includes a first region surrounding the upper region of the channel structure, and a second region surrounding the upper region of the channel structure with the first region interposed therebetween,
wherein a width of the second region is decreased toward the substrate.

13 . The semiconductor device of claim 9 , wherein a width of each of the lower interlayer insulating patterns is increased toward the substrate.

14 . The semiconductor device of claim 9 , wherein a width of a lower pattern among the upper interlayer insulating patterns is larger than a width of an upper pattern among the upper layer insulation patterns disposed to be further from the substrate than the lower pattern.

15 . The semiconductor device of claim 9 , further comprising:
a memory layer formed to be in contact with an external wall of the channel structure to surround the channel structure.

16 . The semiconductor device of claim 9 , further comprising:
a memory layer configured to surround each of the upper conductive patterns and the lower conductive patterns.

17 . A semiconductor device, comprising:
lower interlayer insulating patterns and lower conductive patterns alternately stacked on a substrate; upper interlayer insulating patterns and upper conductive patterns alternately stacked on the lower interlayer insulating patterns and the lower conductive patterns; and a channel structure including an upper region, which passes through the upper interlayer insulating patterns and the upper conductive patterns and has a lateral wall inclined at a first angle with respect to a surface of the substrate, and a lower region, which passes through the lower interlayer insulating patterns and the lower conductive patterns and has a lateral wall inclined at a second angle with respect to the surface of the substrate, in which the first angle is closer to 90° than the second angle.

18 . The semiconductor device of claim 17 , further comprising:
upper oxide layer patterns interposed between the upper region and the upper interlayer insulating patterns, spaced apart with any one of the upper conductive patterns interposed therebetween, and having widths decreased toward the substrate; and lower oxide layer patterns interposed between the lower region and the lower interlayer insulating patterns, and spaced apart with any one of the lower conductive patterns interposed therebetween.

19 . The semiconductor device of claim 18 , wherein each of the upper oxide layer patterns includes a first region surrounding the upper region, and a second region surrounding the upper region with the first region interposed therebetween and having one of the widths decreased toward the substrate.

20 . The semiconductor device of claim of claim 17 , wherein the upper and lower interlayer insulating patterns are formed of a denser film quality than a region of upper oxide layer patterns.

21 . The semiconductor device of claim 17 , wherein the upper interlayer insulating patterns are formed with a same width.

22 . The semiconductor device of claim 17 , further comprising:
a semiconductor layer within the channel structure wherein a thickness of the semiconductor layer is configured to be uniform.

23 . The semiconductor device of claim 17 , wherein a width difference between the upper conductive patterns formed on planes having different heights is decreased.

24 . The semiconductor device of claim 17 , wherein a width difference between the upper conductive patterns and the lower conductive patterns is decreased.

25 . The semiconductor device of claim 17 , further comprising:
a hole opened by a tapered layer, wherein a width difference between an upper region of the hole and a lower region of the hole is decreased.

26 . The semiconductor device of claim 25 , wherein the tapered layer is annealed.

27 . The semiconductor device of claim 17 , wherein a width difference of the channel structure is decreased according to a height of the channel structure.

28 . The semiconductor device of claim 17 , wherein the upper region of the channel structure is configured to have the lateral wall be closer to the surface of the substrate as compared to the lower region of the channel str

Assignees

• Sk Hynix Inc

Inventors

• Lee Yang Bok
• Kim Ji Seong
• Choi Sung Ho

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title