Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9099348-B2
Application number	US-201213602038-A
Country	US
Kind code	B2
Filing date	Aug 31, 2012
Priority date	Feb 1, 2012
Publication date	Aug 4, 2015
Grant date	Aug 4, 2015

Abstract

A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity.

First claim

What is claimed is:

1. A semiconductor device comprising:
vertical channel layers;
a pipe channel layer configured to connect lower ends of the vertical channel layers; and
a pipe gate surrounding the pipe channel layer and including a first conductive layer and a second conductive layer,
wherein the first conductive layer includes a first region contacting a lower surface and a side surface of the pipe channel layer and remaining second regions, wherein the first region includes a first-type impurity, and the remaining second regions include a second-type impurity different from the first-type impurity,
the second conductive layer formed on the first conductive layer and including the first-type impurity, and
the vertical channel layers pass through the second conductive layer.

2. The semiconductor device of claim 1 , wherein the first conductive layer is formed of a poly silicon layer, the first region includes a P-type impurity, and the remaining second regions include an N-type impurity; and
wherein the second conductive layer is formed of a poly silicon layer including the P-type impurity.

3. The semiconductor device of claim 1 , further comprising a first contact plug connected to the second conductive layer.

4. The semiconductor device of claim 1 , further comprising a first contact plug passing through the second conductive layer and directly connected to the remaining second regions of the first conductive layer.

5. The semiconductor device of claim 1 , further comprising:
a gate insulating layer formed on a substrate; and
a gate electrode formed on the gate insulating layer and including a first conductive layer and a second conductive layer stacked on the first conductive layer, wherein the first conductive layer includes the second-type impurity and the second conductive layer includes the first-type impurity.

6. The semiconductor device of claim 5 , further comprising a second contact plug connected to the second conductive layer of the gate electrode.

7. The semiconductor device of claim 5 , further comprising a second contact plug passing through the second conductive layer of the gate electrode and directly connected to the first conductive layer of the gate electrode.

8. The semiconductor device of claim 5 , wherein the first conductive layer is formed of an N-type poly silicon layer and the second conductive layer is formed of a P-type poly silicon layer.

9. The semiconductor device of claim 5 , wherein the first conductive layer of the gate electrode directly contacts the second conductive layer of the gate electrode.

10. A semiconductor device comprising:
a pipe gate;
word lines stacked on the pipe gate; and
pipe channel layers formed in the pipe gate,
wherein the pipe gate includes first regions, which surround the pipe channel layer and include a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity, and
the first regions directly contact the remaining second regions.

11. The semiconductor device of claim 10 , wherein the first regions are defined to surround the pipe channel layers, respectively, and the remaining second regions are defined between neighbored pipe channels and under the pipe channels to surround the first regions and isolate the first regions from each other.

12. The semiconductor device of claim 1 , further comprising:
a memory layer surrounding the vertical channel layers and the pipe channel layer.

13. The semiconductor device of claim 1 , wherein the second conductive layer contacts the memory formed on a top surface of the pipe channel layer.

Assignees

• Lee Ki Hong
• Pyi Seung Ho
• Shon Hyun Soo
• Sk Hynix Inc

Inventors

• Lee Ki Hong
• Pyi Seung Ho
• Shon Hyun Soo

Classifications

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H10B43/40 Primary

  characterised by the peripheral circuit region · CPC title