Method of making a three-dimensional memory device having a heterostructure quantum well channel

Patent metadata

Field	Value
Publication number	US-2016358933-A1
Application number	US-201514733335-A
Country	US
Kind code	A1
Filing date	Jun 8, 2015
Priority date	Jun 8, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.

First claim

What is claimed is:

1 . A method of forming a monolithic three-dimensional memory device, comprising:
forming a stack of alternating layers comprising first material layers and second material layers over a substrate; forming a memory opening through the stack of alternating layers; forming a memory film in the memory opening; forming a first semiconductor material layer having a first band gap over the memory film; and forming a second semiconductor material layer having a second band gap that is narrower than the first band gap over the first semiconductor material layer, wherein a heterostructure quantum well is formed at an interface between the first semiconductor material layer and the second semiconductor material layer.

2 . The method of claim 1 , wherein:
the first semiconductor material layer and the second semiconductor material layer collectively constitute a semiconductor channel; a conduction band of the semiconductor channel has a minimum along a radial direction at, or in proximity to, the interface; a quantum well containing two-dimensional electron gas for electrical current conduction is formed at, or in proximity to, an interface between the first semiconductor material layer and the second semiconductor material layer; a heterojunction is formed between two different semiconductor materials at the interface between the first semiconductor material layer and the second semiconductor material layer; and the heterojunction has a configuration of a cylindrical sheet having a substantially uniform horizontal cross-sectional shape.

3 . The method of claim 1 , wherein:
the first semiconductor material layer comprises a first III-V compound semiconductor material; and the second semiconductor material layer comprises a second III-V compound semiconductor material.

4 . The method of claim 3 , wherein:
the first compound semiconductor material is undoped; and the second compound semiconductor material is undoped.

5 . The method of claim 3 , wherein:
the first semiconductor material layer is formed by depositing an n-doped first compound semiconductor material layer as an outer portion and subsequently depositing an undoped first compound semiconductor material layer as an inner portion; and the second semiconductor material layer is formed by depositing an undoped second compound semiconductor material layer.

6 . The method of claim 3 , wherein:
the first semiconductor material layer is formed by depositing an undoped first compound semiconductor material layer as an outer portion and subsequently forming n-type delta doped first compound semiconductor material layer as an inner portion; and the second semiconductor material layer is formed by depositing an undoped second compound semiconductor material layer.

7 . The method of claim 3 , wherein:
the first semiconductor material layer is formed by depositing an undoped first compound semiconductor material layer as an outer portion, forming n-type delta doped first compound semiconductor material layer as an intermediate portion, and depositing an additional first compound semiconductor material layer as an inner portion of the first semiconductor material layer; and the second semiconductor material layer is formed by depositing an undoped second compound semiconductor material layer.

8 . The method of claim 3 , wherein the first and second III-V compound semiconductor materials comprise single crystalline or large grain polycrystalline materials having an average grain size greater than 300 nm along at least one direction.

9 . The method of claim 8 , wherein:
the first semiconductor material layer is deposited over a Group III nucleation layer; the first semiconductor material layer is deposited at a higher temperature than the second semiconductor material layer; and respective first and second self annealing steps are performed after the respective first and second semiconductor material layers are deposited.

10 . The method of claim 3 , wherein:
the first III-V compound semiconductor material comprises a material selected from AlGaAs, GaAs, InAlAs, and InGaAlAs; and the second III-V compound semiconductor material comprises a material selected from GaAs, InGaAs, InP, InAs, and InGaAsP.

11 . The method of claim 1 , wherein:
forming the memory film comprises forming charge storage elements comprising a charge trapping material, and forming a tunneling dielectric layer on an inner sidewall of the charge storage elements. the tunneling dielectric layer comprises a lateral stack of a plurality of dielectric material layers including at least one high-k dielectric material layer; an outermost tunneling dielectric layer within the lateral stack comprises silicon oxide; an innermost tunneling dielectric layer within the lateral stack comprises aluminum oxide; and the lateral stack is formed by depositing at least one intermediate tunneling dielectric layer after formation of the outermost tunneling dielectric layer and prior to formation of the innermost tunneling dielectric layer.

12 . The method of claim 11 , wherein:
each of the at least one intermediate tunneling dielectric layer is selected from a silicon nitride layer, a lanthanum oxide layer, a hafnium oxide layer, a zirconium oxide layer, and a silicon oxynitride layer; and forming the memory film further comprises forming a blocking dielectric layer on a sidewall of the memory opening, wherein the charge storage elements are formed on the blocking dielectric layer.

13 . The method of claim 1 , further comprising forming an epitaxial single crystal pedestal at a bottom portion of the memory opening, wherein the memory film is formed over, and on, the epitaxial pedestal, wherein each of the first semiconductor material layer and the second semiconductor material layer is formed as a single crystalline or polycrystalline III-V compound semiconductor material layer.

14 . The method of claim 13 , wherein the single crystal material of the pedestal is different in composition from the III-V compound semiconductor material.

15 . The method of claim 14 , wherein the single crystal material of the pedestal comprises single crystalline silicon.

16 . The method of claim 13 , wherein the single crystal material of the pedestal comprises a III-V semiconductor material that is the same in composition as the first or the second semiconductor material layers.

17 . The method of claim 1 , further comprising:
forming a drain region at an upper portion of the second semiconductor material layer; forming a source region located in the substrate and laterally spaced from the memory opening; forming a backside contact trench through the stack of alternating layers; and forming backside recesses by removing the second material layers selective to the first material layers employing an etchant introduced into the backside contact trench; and forming electrically conductive layers in the backside recesses, wherein the first material layers are insulator layers, and an alternating stack of the insulator layers and the electrically conductive layers is formed; forming an insulating spacer in the backside contact trench after formation of the alternating stack; and forming a contact via structure within a cavity inside the insulating spacer.

18 . The method of claim 17 , wherein forming the drain region comprises doping an upper part of the second semiconductor material layer to form a doped III-V compound semiconductor material drain extension region contacting an upper

Assignees

• Sandisk Technologies Inc

Inventors

• Rabkin Peter
• Pachamuthu Jayavel
• Alsmeier Johann
• Higashitani Masaaki

Classifications

• H10P14/3448

  Delta-doping · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69396

  the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title