Semiconductor Package with Multi-Section Conductive Carrier
US-2016240461-A1 · Aug 18, 2016 · US
Method for fabricating a semiconductor package with conductive carrier integrated heat spreader
US9673109B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9673109-B2 |
| Application number | US-201615019318-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 9, 2016 |
| Priority date | Oct 18, 2012 |
| Publication date | Jun 6, 2017 |
| Grant date | Jun 6, 2017 |
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- Title
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- Abstract
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- First independent claim
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Abstract
Official abstract text for this publication.
In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method for fabricating a semiconductor package, said method comprising: providing a conductive carrier having a die side and an opposite input/output (I/O) side; providing a control FET and a sync FET of a power converter switching stage, said control FET having a control drain and said sync FET having a sync source; attaching said control drain of said control FET and said sync source of said sync FET to said die side of said conductive carrier; forming a control conductive carrier attached to said control drain and a sync conductive carrier attached to said sync source. 2. The method of claim 1 , wherein said conductive carrier comprises a lead frame. 3. The method of claim 1 , wherein said conductive carrier is pre-patterned. 4. The method of claim 1 , wherein said control FET and said sync FET comprise silicon FETs. 5. The method of claim 1 , wherein said control FET and said sync FET comprise III-Nitride FETs. 6. The method of claim 1 , wherein said power converter switching stage is a part of a buck converter. 7. A method for fabricating a semiconductor package, said method comprising: providing a conductive carrier having a die side and an input/output (I/O) side; providing a control FET and a sync FET, said control FET having a control drain and said sync FET having a sync source; attaching said control drain of said control FET and said sync source of said sync FET to said die side of said conductive carrier; forming a control conductive carrier attached to said control drain. 8. The method of claim 7 , wherein said conductive carrier comprises a lead frame. 9. The method of claim 7 , wherein said conductive carrier is pre-patterned. 10. The method of claim 7 , wherein said control FET and said sync FET comprise silicon FETs. 11. The method of claim 7 , wherein said control FET and said sync FET comprise III-Nitride FETs. 12. The method of claim 7 , wherein said control FET and said sync FET are part of a power converter switching stage. 13. The method of claim 12 , wherein said power converter switching stage is part of a buck converter. 14. A method for fabricating a semiconductor package, said method comprising: providing a conductive carrier having a die side and an input/output (I/O) side; providing a control FET and a sync FET, said control FET having a control drain and said sync FET having a sync source; attaching said control drain of said control FET and said sync source of said sync FET to said die side of said conductive carrier; forming a sync conductive carrier attached to said sync source. 15. The method of claim 14 , wherein said conductive carrier comprises a lead frame. 16. The method of claim 14 , wherein said conductive carrier is pre-patterned. 17. The method of claim 14 , wherein said control FET and said sync FET comprise silicon FETs. 18. The method of claim 14 , wherein said control FET and said sync FET comprise III-Nitride FETs. 19. The method of claim 14 , wherein said control FET and said sync FET are part of a power converter switching stage. 20. The method of claim 19 , wherein said power converter switching stage is part of a buck converter.
Assignees
Inventors
Classifications
characterised by their shape or disposition · CPC title
of die-attach connectors · CPC title
Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title
of bump connectors · CPC title
On different surfaces · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9673109B2 cover?
- In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conducti…
- Who is the assignee on this patent?
- Infineon Technologies Americas Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W70/481. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 06 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).