Power converter package including vertically stacked driver IC

Patent metadata

Field	Value
Publication number	US-9159703-B2
Application number	US-201314023038-A
Country	US
Kind code	B2
Filing date	Sep 10, 2013
Priority date	Oct 18, 2012
Publication date	Oct 13, 2015
Grant date	Oct 13, 2015

Abstract

In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.

First claim

The invention claimed is:

1. A semiconductor package comprising:
a control conductive carrier having a die side and an opposite input/output (I/O) side connecting said semiconductor package to a mounting surface;
a control FET of a power converter switching stage attached to said die side of said control conductive carrier;
a driver integrated circuit (IC) for driving said control FET, said driver IC situated above said control FET and electrically coupled to said control FET by at least one conductive buildup layer formed over said control conductive carrier.

2. The semiconductor package of claim 1 , further comprising a sync conductive carrier having another die side and another opposite input/output (I/O) side connecting said semiconductor package to said mounting surface;
a sync FET of said power converter switching stage attached to said another die side of said sync conductive carrier.

3. The semiconductor package of claim 1 , wherein said driver IC is electrically coupled to said at least one conductive buildup layer formed over said control conductive carrier by bondwire.

4. The semiconductor package of claim 1 , wherein said driver IC is flip chip mounted above said at least one conductive buildup layer formed over said control conductive carrier.

5. The semiconductor package of claim 1 , wherein said control FET comprises a silicon FET.

6. The semiconductor package of claim 1 , wherein said control FET comprises a III-Nitride FET.

7. The semiconductor package of claim 1 , wherein said power converter switching stage is implemented as part of a buck converter.

8. A semiconductor package comprising:
a sync conductive carrier having a die side and an opposite input/output (I/O) side connecting said semiconductor package to a mounting surface;
a sync FET of a power converter switching stage attached to said die side of said sync conductive carrier;
a driver integrated circuit (IC) for driving said sync FET, said driver IC situated above said sync FET and electrically coupled to said sync FET by at least one conductive buildup layer formed over said sync conductive carrier.

9. The semiconductor package of claim 8 , further comprising a control conductive carrier having another die side and another opposite input/output (I/O) side connecting said semiconductor package to said mounting surface;
a control FET of said power converter switching stage attached to said another die side of said control conductive carrier.

10. The semiconductor package of claim 8 , wherein said driver IC is electrically coupled to said at least one conductive buildup layer formed over said sync conductive carrier by bondwire.

11. The semiconductor package of claim 8 , wherein said driver IC is flip chip mounted above said at least one conductive buildup layer formed over said sync conductive carrier.

12. The semiconductor package of claim 8 , wherein said sync FET comprises a silicon FET.

13. The semiconductor package of claim 8 , wherein said sync FET comprises a III-Nitride FET.

14. The semiconductor package of claim 8 , wherein said power converter switching stage is implemented as part of a buck converter.

Assignees

• Int Rectifier Corp

Inventors

• Cho Eung San
• Sawle Andrew N
• Pavier Mark
• Cutler Daniel

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title