Method of improving line roughness in substrate processing

US9508557B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9508557-B2
Application numberUS-201514676356-A
CountryUS
Kind codeB2
Filing dateApr 1, 2015
Priority dateNov 24, 2014
Publication dateNov 29, 2016
Grant dateNov 29, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a method for processing a semiconductor substrate to reduce line roughness, the method comprising: positioning a substrate in a film-forming system, the film-forming system comprising a chuck having a clamping mechanism configured to hold the substrate in a processing chamber and flex the substrate by displacing a center of the substrate relative to a peripheral edge of the substrate so as to create a concave surface during processing; coating the substrate with a layer of material; performing a post apply bake process; flexing the substrate to create the concave surface either during the post apply bake or following the post apply bake process, wherein the concave surface has a degree of concavity measured at the center of the substrate that exceeds a base number of microns; and unflexing the substrate and inducing tensile stress in the layer of material on the substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of preparing a thin film, comprising: receiving a substrate having a layer of photoresist applied on the substrate; performing a post application bake process; flexing the substrate to create a concave surface either during the post application bake process or following the post application bake process, wherein the concave surface has a degree of concavity measured at the center of the substrate that exceeds a target, non-zero deflection; and unflexing the substrate and inducing tensile stress in the layer of photoresist on the substrate. 2. The method of claim 1 wherein: the degree of concavity ranges up to 300 microns for a 300 mm substrate. 3. The method of claim 1 wherein: the degree of concavity ranges from 100 microns to 200 microns or wherein the degree of concavity is less than 1 micron per millimeter of diameter of the substrate. 4. The method of claim 1 wherein: the degree of concavity is selected and varied according the diameter of the substrate and historical data acquired for processing the layer of photoresist. 5. The method of claim 1 , wherein the method of preparing the thin film utilizes a track system coupled to a processing chamber, and wherein the processing chamber is one of a coating chamber, a bake chamber, or a developing chamber, or the film-forming system is at least one of a spin-on coating chamber or a vapor deposition chamber. 6. The method of claim 1 , further comprising concurrently controlling two or more operating variables of one or more operations of the method in order to achieve a target reduction in line roughness of the substrate. 7. A method for processing a semiconductor substrate to reduce line roughness, the method comprising: positioning a substrate in a film-processing system, the film-processing system comprising a chuck having a clamping mechanism configured to hold the substrate in a processing chamber and flex the substrate by displacing a center of the substrate relative to a peripheral edge of the substrate so as to create a concave surface during processing, the substrate having a layer of photoresist; performing a first film-processing procedure on the substrate; performing a second film-processing procedure on the substrate; flexing the substrate to create the concave surface either during the second film-processing procedure or following the second film-processing procedure, wherein the concave surface has a degree of concavity measured at the center of the substrate that exceeds a base number of microns; and unflexing the substrate and inducing tensile stress in the layer of photoresist on the substrate. 8. The method of claim 7 , wherein the first-film processing procedure is an exposure process. 9. The method of claim 8 wherein the second film-processing procedure is a post exposure bake procedure. 10. The method of claim 7 , wherein the first-film processing procedure is a development process. 11. The method of claim 10 wherein the second film-processing procedure is a post develop bake procedure. 12. The method of claim 7 : wherein the degree of concavity is modified by the clamping mechanism of the chuck; wherein the clamping mechanism utilizes an electrostatic device to modify the degree of concavity; or wherein the clamping mechanism utilizes a vacuum device to modify the degree of concavity. 13. The method of claim 7 wherein: the degree of concavity is selected and varied according the diameter of the substrate and historical data acquired for processing the layer of photoresist. 14. The method of claim 7 , further comprising concurrently controlling two or more operating variables of one or more operations of the method in order to achieve a target reduction in line roughness of the substrate. 15. A method for processing a semiconductor substrate, the semiconductor having a structure, the structure having a line roughness, the method configured to improve line roughness, the method comprising: positioning a substrate in a track system, the track system comprising a chuck having a clamping mechanism configured to hold the substrate in a processing chamber and flex the substrate by displacing a center of the substrate relative to a peripheral edge of the substrate so as to create a concave surface during processing, the substrate having a layer of photoresist; depositing a spacer layer on the substrate, the deposition generating a spacer pattern on the substrate; flexing the substrate to create the concave surface either during the deposition or following the deposition of the spacer layer, wherein the concave surface has a degree of concavity measured at the center of the substrate that exceeds a base number of microns; and unflexing the substrate and inducing tensile stress in the layer of photoresist on the substrate. 16. The method of claim 15 wherein: the degree of concavity is from a range of 150 to 200 μm or the degree of concavity is less than 1 micron per millimeter of diameter length of the substrate, or the degree of concavity is varied according the diameter of the substrate and historical data acquired for processing the layer of photoresist. 17. The method of claim 16 wherein a target reduction in the line roughness is 4 to 6 nm of 3 sigma (3σ) or wherein the line roughness includes line edge roughness and line width roughness. 18. The method of claim 15 further comprising: performing an etch process on the spacer pattern on the substrate; flexing the substrate to create the concave surface either during the etch process or following the etch process, wherein the concave surface has a degree of concavity measured at the center of the substrate that exceeds a base number of microns; and unflexing the substrate and inducing tensile stress in the spacer pattern on the substrate. 19. The method of claim 15 , further comprising concurrently controlling two or more operating variables of one or more operations of the method in order to achieve a target reduction in line roughness of the substrate; wherein the two or more operating variables include chamber temperature, degree of concavity, and/or duration of flexing operation.

Assignees

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Classifications

  • Thermal treatments, e.g. annealing or sintering · CPC title

  • of organic photoresist masks · CPC title

  • characterised by edge profile or support profile · CPC title

  • Horizontal transfer of a single workpiece · CPC title

  • mainly by convection · CPC title

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What does patent US9508557B2 cover?
Provided is a method for processing a semiconductor substrate to reduce line roughness, the method comprising: positioning a substrate in a film-forming system, the film-forming system comprising a chuck having a clamping mechanism configured to hold the substrate in a processing chamber and flex the substrate by displacing a center of the substrate relative to a peripheral edge of the substrat…
Who is the assignee on this patent?
Tokyo Electron Ltd
What technology area does this patent fall under?
Primary CPC classification H10P52/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).