High speed level translator

Patent metadata

Field	Value
Publication number	US-9503090-B2
Application number	US-201414463136-A
Country	US
Kind code	B2
Filing date	Aug 19, 2014
Priority date	Aug 19, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

First claim

What is claimed:

1. A level translator, comprising:
a resistor divider; and
a one-shot circuit which includes a pull-up stack of transistors in parallel with the resistor divider, and which the one-shot circuit conducts to assist during a transition from a first state to a second state through a conduction path provided by the transistors of the pull-up stack, and is non-conducting during a transition from the second state to the first state,
wherein the resistor divider is switched on/off to provide an output at two different levels of VPP2 and VPP, where VPP2 is a low voltage for an inverter chain and VPP is the low voltage inverted to a high voltage,
wherein the one-shot circuit translates from the low voltage to the high voltage using the transistors arranged in parallel with a first resistor of the resistor divider, and
wherein the one-shot circuit is comprised of an inverter chain having outputs controlling gates of the transistors which are arranged in series, with one another, to provide a conduction path between an output level of the first resistor of the resistor divider.

2. The level translator of claim 1 , wherein the transistors of the one-shot circuit are provided with a feedback loop to improve switching performance in a direction serviced by a resistor pull up.

3. The level translator of claim 1 , wherein a 4-level translator circuit translates input signals from Gnd/Vdd to output levels VPP2/VPP where FET voltage stress is limited to Vdd level.

4. The level translator of claim 1 , wherein the resistor divider comprises a first resistor R 0 and a second resistor R 1 , in series, which is enabled by transistors T 0 and T 1 , the transistor T 1 is a series stack device to limit stress across transistor T 0 to Vdd.

5. The level translator of claim 4 , wherein resistive values of the resistors R 0 and R 1 are chosen to output voltage signal V 2 IN of approximately the VPP2 when the transistor T 0 receives a Vdd level logic input signal, and when the resistor divider is disabled, the voltage signal V 2 IN is approximately the VPP.

6. The level translator of claim 5 , wherein:
the one-shot circuit comprises the pull-up stack comprising the transistors, in series, which allows conduction from the low voltage VPP to the voltage signal V 2 IN;
the pull-up stack is enabled during transition of low-to-high switching which increases switching speed; and
the pull-up stack is disabled when low-to-high switching is complete such that a subsequent high-to low transition is unimpeded by the pull-up stack.

7. The level translator of claim 6 , wherein the one-shot circuit further comprises an inverter chain comprising inverters.

8. The level translator of claim 7 , wherein the inverters are connected in series to establish a pull-up gate signal and its complement to the transistors.

9. A level translator, comprising:
a resistor divider comprising a first resistor and a second resistor, in series; and
a one-shot circuit comprising a first transistor and a second transistor which comprise a pull-up stack, in series, the pull-up stack in parallel with the resistor divider, and an inverter chain providing control to the first transistor and the second transistor.

10. The level translator of claim 9 , wherein the first transistor and the second transistor are controlled to conduct during a transition from a first state to a second state, and non-conduct during a transition from the second state to the first state.

11. The level translator of claim 10 , wherein the inverter chain has outputs which control gates of the first transistor and the second transistor.

12. The level translator of claim 11 , wherein:
a first output node of the inverter chain is initially at a level so the first transistor is off;
a second output node of the inverter chain is initially at a level so the second transistor is on; and
the one-shot circuit receives an input signal, which is propagated to the first and second output nodes such that the pull-up stack comprising the first transistor and the second transistor pulls up an input voltage by first turning on the first transistor and subsequently turning off the second transistor after the input signal propagates to the second output node.

13. The level translator of claim 12 , wherein the first resistor has a larger resistive value than the second resistor and the first resistor is in parallel with the pull-up stack.

14. The level translator of claim 12 , wherein the pull-up stack is switched off before an input node is reversed to prevent a slow down on pull-down time.

15. The level translator of claim 12 , wherein resistor divider is enabled by transistors T 0 and T 1 .

16. The level translator of claim 15 , wherein the transistor T 1 is a series stack device to limit stress across transistor T 0 to Vdd.

17. A method comprising:
controlling transistors of a pull-up stack of a one-shot circuit such that the pull-up stack conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state, wherein the transistors are controlled through an inverter chain; and
controlling a resistor divider,
wherein the resistor divider is switched on/off to provide an output at two different levels VPP2 and VPP,
wherein the one-shot circuit translates from a low voltage to high voltage domain using transistors arranged in parallel with a first resistor of the resistor divider, and
wherein the one-shot circuit is comprised of an inverter chain having outputs controlling gates of the transistors which are arranged in series, with one another, to provide a conduction path between an output level of the first resistor of the resistor divider.

Assignees

• IBM

Inventors

• Fifield John A

Classifications

• H03K19/01855 Primary

  synchronous, i.e. using clock signals · CPC title

• H03K19/0944

  using MOSFET {or insulated gate field-effect transistors, i.e. IGFET}(H03K19/096 takes precedence) · CPC title

• H03K19/01742 Primary

  by means of a pull-up or down element · CPC title