Interface circuit and electronic system using the same

Patent metadata

Field	Value
Publication number	US-9419618-B1
Application number	US-201514811476-A
Country	US
Kind code	B1
Filing date	Jul 28, 2015
Priority date	May 28, 2015
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

An interface circuit applied in an electronic system includes a first control circuit and a second control circuit. The first control circuit includes a first control chip, a first voltage division unit, a switch unit, and a first connector. The second control circuit includes a second control chip, a second voltage division unit, a third voltage division unit, and a second connector. When the serial data pin or the serial clock pin first control chip outputs a first voltage level signal, the serial data pin or the serial clock pin second control chip receives the first voltage level signal. When the serial data pin or the serial clock pin first control chip outputs a second voltage level signal, the serial data pin or the serial clock pin second control chip receives a second voltage level signal from a power source terminal.

First claim

What is claimed is:

1. An interface circuit comprising:
a first control circuit comprising a first control chip, a first transmission unit electrically coupled to the first control chip, and a first connector electrically coupled to the first transmission unit, the first transmission unit comprising:
a first voltage division unit electrically coupled to the first control chip and a first power source terminal, and a switch unit electrically coupled to the first control chip, the first voltage division unit, and the first connector;

a second control circuit comprising a second control chip, a second transmission unit electrically coupled to the second control chip, and a second connector electrically coupled to the second transmission unit and the first connector, the second transmission unit comprising:
a second voltage division unit electrically coupled to the second control chip and a second power source terminal, and a third voltage division unit electrically coupled to the second control chip, the second voltage division unit, and the second connector;

wherein each of the first and second control chips comprises a serial data pin and a serial clock pin, the first and second control chips configured such that in event that the serial data pin or the serial clock pin of the first control chip outputs a first control signal, the switch unit of the first transmission unit is turned on, and the first control signal is transmitted to the serial data pin or the serial clock pin of the second control chip through the first connector, the second connector, and the third voltage division unit of the second transmission unit; and
wherein the first and second control chips are configured such that in event that the serial data pin or the serial clock pin of the first control chip outputs a second control signal, the switch unit of the first transmission unit is turned off, and the serial data pin or the serial clock pin of the second control chip receives a voltage of the second power source terminal through the second voltage division unit.

2. The interface circuit of claim 1 , wherein in event that the serial data pin or the serial clock pin of the second control chip outputs a third control signal, the switch unit of the first transmission unit is turned on, the first control signal is transmitted to the serial data pin or the serial clock pin of the first control chip through the third voltage division unit of the second transmission, the second connector, and the first connector; and in event that the serial data pin or the serial clock pin of the second control chip outputs a fourth control signal, the switch unit of the first transmission unit is turned off, the serial data pin or the serial clock pin of the first control chip receives a voltage of the first power source terminal through the first voltage division unit.

3. The interface circuit of claim 2 , wherein in event that the serial data pin of the first control chip outputs a digital low level signal, the first electronic switch and the first diode are turned on, the serial data pin of the first control chip transmits the digital low level signal to the serial data pin of the second control chip through the first and second connectors; in event that the serial data pin of the first control chip outputs a digital high level signal, the first electronic switch and the first diode are turned off, the serial data pin of the second control chip receives the voltage of the second power source terminal through the seventh resistor; when the serial data pin of the second control chip outputs a digital low level signal, the first diode is turned on, the first electronic switch is turned on, the digital low level signal from the serial data pin of the second control chip is transmitted to the serial data pin of the first control chip through the first and second connector; when the serial data pin of the second control chip outputs a digital high level signal, the first electronic switch and the first diode are turned off, the serial data pin of the first control chip receives the voltage of the first power source terminal through the first resistor.

4. The interface circuit of claim 1 , wherein the first voltage division unit of the first transmission unit comprises first and second resistors, the switch unit comprises third to sixth resistors, a first electronic switch, a second electronic switch, a first diode and a second diode; the second voltage division unit of the second transmission unit comprises seventh and eighth resistors, the third voltage division unit comprises ninth and tenth resistors, the serial data pin and the serial clock pin of the first control chip are electrically coupled to the first power source terminal respectively through the first and second resistors; a first terminal of the first electronic switch is electrically coupled to the first power source terminal, a second terminal of the first electronic switch is electrically coupled to the serial data pin of the first control chip, a third terminal of the first electronic switch is electrically coupled to a cathode of the first diode through the fourth resistor; a first terminal of the second electronic switch is electrically coupled to the first power source terminal through the fifth resistor, a second terminal of the second electronic switch is electrically coupled to the serial clock pin of the first control chip, a third terminal of the second electronic switch is electrically coupled to a cathode of the second diode through the sixth resistor, anodes of the first and second diodes are electrically coupled to the first power source terminal; a first pin of the first connector is electrically coupled to the third terminal of the second electronic switch, a second pin of the first connector is grounded, a third pin of the first connector is electrically coupled to the third terminal of the first electronic switch; the serial data pin of the second control chip is electrically coupled to the second power source terminal through the seventh resistor, and is electrically coupled to a third pin of the second connector through the eighth resistor; the serial clock pin of the second control chip is electrically coupled to the second power source terminal through the ninth resistor, and is electrically coupled to a first pin of the second connector through the tenth resistor; a second pin of the second connector is electrically coupled to ground; the first to third pins of the first connector are electrically coupled to the first to third pins of the second connector.

5. The interface circuit of claim 4 , wherein the first transmission unit comprises a first capacitor and a second capacitor, the first terminal of the first electronic switch is grounded through the first capacitor, and the first terminal of the second switch is grounded through the second capacitor.

6. The interface circuit of claim 4 , wherein the first and second electronic switches are n-channel metal oxide semiconductor field-effect transistors (NMOSFETs), the first to third terminals of each electronic switch correspond to a gate, a source, and a drain of the NMOSFET respectively.

7. The interface circuit of claim 1 , wherein the first and second control chips are inter-integrated circuit (I2C) control chip.

8. An electronic system comprising an interface circuit, the interface circuit comprising a motherboard and a system board, the motherboard comprising:
a first control circuit comprising a first control chip, a first transmission unit electrically coupled to the first control chip, and a first connector electrically coupled to the first transmission unit, the first transmission unit comprising:
a first voltage division unit electrically coupled to the first control chip and a fi

Assignees

• Hong Fu Jin Prec Ind (Shenzhen) Co Ltd
• Hon Hai Prec Ind Co Ltd

Inventors

• Zheng sheng-cun

Classifications

• H03K19/01855 Primary

  synchronous, i.e. using clock signals · CPC title