Semiconductor device and semiconductor device control method

Patent metadata

Field	Value
Publication number	US-2016285455-A1
Application number	US-201615081154-A
Country	US
Kind code	A1
Filing date	Mar 25, 2016
Priority date	Mar 26, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

There is provided a semiconductor device including (1) a first power source section that includes a first power source output terminal and a second power source output terminal that output voltages at mutually different voltage levels, (2) a first output section that includes a first output stage switch that is provided between the first power source output terminal and a first voltage output terminal, and a second output stage switch that is provided between the second power source output terminal and the first power source output terminal, and (3) a controller that performs ON/OFF control of the first output stage switch and the second output stage switch such that both the first output stage switch and the second output stage switch are in an OFF state over a predetermined period encompassing a point in time when a signal level of the first signal switches.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first power source section that includes a first power source output terminal and a second power source output terminal that output voltages at mutually different voltage levels, the first power source section changing the respective voltage levels output from the first power source output terminal and the second power source output terminal according to switching of a signal level of a first signal; a first output section that includes a first output stage switch that is provided between the first power source output terminal and a first voltage output terminal, and a second output stage switch that is provided between the second power source output terminal and the first power source output terminal; and a controller that performs ON/OFF control of the first output stage switch and the second output stage switch such that both the first output stage switch and the second output stage switch are in an OFF state over a predetermined period encompassing a point in time when a signal level of the first signal switches.

2 . The semiconductor device of claim 1 , wherein
the first power source section includes:
a first power source switch that is provided between a first power source line producing a first voltage, and the first power source output terminal;
a second power source switch that is provided between a second power source line producing a second voltage smaller than the first voltage, and the first power source output terminal;
a third power source switch that is provided between a third power source line producing a third voltage smaller than the second voltage, and the second power source output terminal;
a fourth power source switch that is provided between a fourth power source line producing a fourth voltage smaller than the third voltage, and the second power source output terminal; and
a switching control section that, according to a switch in the signal level of the first signal, switches one out of the first power source switch or the second power source switch to an OFF state, and switches the other out of the first power source switch or the second power source switch to an ON state, and switches one out of the third power source switch or the fourth power source switch to an OFF state and the other out of the third power source switch or the fourth power source switch to an ON state.

3 . The semiconductor device of claim 2 , wherein:
the switching control section includes a timing regulation circuit that performs ON/OFF switching of the first power source switch and ON/OFF switching of the second power source switch at different timings from each other, and that performs ON/OFF switching of the third power source switch and ON/OFF switching of the fourth power source switch at different timings from each other.

4 . The semiconductor device of claim 2 , wherein
the predetermined period during which both the first output stage switch and the second output stage switch adopt an OFF state encompasses a period from start to finish of ON/OFF switching of the first to the fourth power source switches.

5 . The semiconductor device of claim 1 , wherein
the predetermined period during which both the first output stage switch and the second output stage switch adopt an OFF state encompasses periods immediately preceding and following a point in time when the signal level of the first signal switches.

6 . The semiconductor device of claim 1 , wherein
the first signal is a signal synchronized with a clock signal; and both the first output stage switch and the second output stage switch adopt an OFF state synchronized with the clock signal, and the predetermined period during which both the first output stage switch and the second output stage switch adopt an OFF state is a period corresponding to one cycle of the clock signal.

7 . The semiconductor device of claim 1 , wherein
the controller includes:
a first signal generator that generates the first signal; and
a second signal generator that generates a second signal for ON/OFF controlling the first output stage switch and a third signal for ON/OFF controlling the second output stage switch.

8 . The semiconductor device of claim 1 , wherein:
the first output section includes a plurality of first output stage switches provided between the first power source output terminal and a plurality of the respective first voltage output terminals, and a plurality of second output stage switches provided between the second power source output terminal and the plurality of respective first voltage output terminals; and the controller performs ON/OFF control of the plurality of respective first output stage switches and the plurality of respective second output stage switches such that the plurality of respective first output stage switches and the plurality of respective second output stage switches adopt an OFF state over a predetermined period encompassing a point in time when the signal level of the first signal switches.

9 . The semiconductor device of claim 1 , further comprising:
a second power source section that includes a third power source output terminal and a fourth power source output terminal that output voltages at mutually different voltage levels, the second power source section changing the respective voltage levels output from the third power source output terminal and the fourth power source output terminal according to switching of the signal level of the first signal; and a second output section that includes a third output stage switch provided between the third power source output terminal and a second voltage output terminal, and a fourth output stage switch provided between the fourth power source output terminal and the second voltage output terminal, wherein the controller performs ON/OFF control of the third output stage switch and the fourth output stage switch such that both the third output stage switch and the fourth output stage switch are in an OFF state over a predetermined period encompassing a point in time when the signal level of the first signal switches.

10 . The semiconductor device of claim 9 , wherein:
the second output section includes a plurality of third output stage switches provided between the third power source output terminal and a plurality of the respective second voltage output terminals, and a plurality of fourth output stage switches provided between the fourth power source output terminal and the plurality of respective second voltage output terminals; and the controller ON/OFF performs control of the plurality of respective third output stage switches and the plurality of respective fourth output stage switches such that the plurality of respective third output stage switches and the plurality of respective fourth output stage switches adopt an OFF state over a predetermined period encompassing a point in time when the signal level of the first signal switches.

11 . A control method of a semiconductor device including a power source section that includes a first power source output terminal and a second power source output terminal that output voltages at mutually different voltage levels, the power source section changing the respective voltage levels output from the first power source output terminal and the second power source output terminal according to switching of a signal level of a first signal, and an output section that includes a first output stage switch that is provided between the first power source output terminal and a voltage output terminal, and a second output stage switch that is provided between the second power source output terminal and the voltage output terminal,

Assignees

• Lapis Semiconductor Co Ltd

Inventors

• Yamashita Takashi

Classifications

• G09G3/36 Primary

  using liquid crystals · CPC title

• G09G3/3614

  Control of polarity reversal in general · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3681

  suitable for passive matrices only · CPC title

• H03K19/018507 Primary

  Interface arrangements · CPC title