Low power driver with programmable output impedance

Patent metadata

Field	Value
Publication number	US-9490805-B2
Application number	US-201414475544-A
Country	US
Kind code	B2
Filing date	Sep 2, 2014
Priority date	Sep 2, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A programmable low power driver permits an output impedance of the driver to be programmed. Programmability permits the driver output impedance to match an impedance of a transmission line that is connected thereto. The low power driver includes a first driver output and a plurality of driver legs. The programmable low power driver is configured to electrically couple one or more driver legs of the plurality of driver legs to the first driver output to establish an output impedance for the driver.

First claim

What is claimed is:

1. A programmable low power driver, comprising:
a first driver output;
a first programmable driver leg having a pull-up half and a pull-down half, the pull-up half is electrically coupled between a supply voltage and the first driver output, the pull-up half is electrically coupled to receive a signal and a first control signal, the pull-down half is electrically coupled between an internal ground and the first driver output, the pull-down half is electrically coupled to receive an inversion of the signal and the first control signal;
a second programmable driver leg having a pull-up half and a pull-down half, the pull-up half is electrically coupled between the supply voltage and the first driver output, the pull-up half is electrically coupled to receive the signal and a second control signal, the pull-down half is electrically coupled between the internal ground and the first driver output, the pull-down half is electrically coupled to receive the inversion of the signal and the second control signal;
the first programmable driver leg contributes to an output impedance of the first driver output when the first control signal is high and does not contribute to the output impedance of the first driver output when the first control signal is low; and
the second programmable driver leg contributes to the output impedance of the first driver output when the second control signal is high and does not contribute to the output impedance of the first driver output when the second control signal is low.

2. The programmable low power driver of claim 1 , the pull-down half of the first programmable driver leg further comprising:
a first termination resistor having a first end and a second end, the first end is electrically coupled to the internal ground;
a first logical element, having a first input, a second input, and an output, the first input is electrically coupled to receive the inverted signal and the second input is electrically coupled to receive the first control signal; and
a first NMOS device having a source, a drain, and a gate, the gate is electrically coupled to the output of the first logical element, the drain is electrically coupled to the first driver output and the source is electrically coupled to the second end of the first termination resistor; and the pull-up half of the first programmable driver leg further comprising:
a second termination resistor having a first end and a second end, the first end is electrically coupled to a supply voltage;
a second logical element, having a first input, a second input, and an output, the first input is electrically coupled to receive the signal and the second input is electrically coupled to receive the first control signal; and
a second NMOS device having a source, a drain, and a gate, the gate is connected to the output of the second logical element, the drain is electrically coupled to the second end of the second termination resistor, the source is electrically coupled to the first driver output, the pull-down half of the second programmable driver leg further comprising:
a third termination resistor having a first end and a second end, the first end is electrically coupled to the internal ground;
a third logical element, having a first input, a second input, and an output, the first input is electrically coupled to receive the inverted signal and the second input is electrically coupled to receive the second control signal; and
a third NMOS device having a source, a drain, and a gate, the gate is connected to the output of the third logical element, the drain is electrically coupled to the first driver output and the source is electrically coupled to the second end of the third termination resistor; and the pull-up half of the second programmable driver leg further comprising:
a fourth termination resistor having a first end and a second end, the first end is electrically coupled to the supply voltage;
a fourth logical element, having a first input, a second input, and an output, the first input is electrically coupled to receive the signal and the second input is electrically coupled to receive the second control signal; and
a fourth NMOS device having a source, a drain, and a gate, the gate is connected to the output of the fourth logical element, the drain is electrically coupled to the second end of the fourth termination resistor, the source is electrically coupled to the first driver output.

3. The programmable low power driver of claim 2 , further comprising:
a second driver output;
a third programmable driver leg having a pull-up half and a pull-down half, the pull-up half is electrically coupled between the supply voltage and the second driver output, the pull-up half is electrically coupled to receive the inversion of the signal and the first control signal, the pull-down half is electrically coupled between the internal ground and the second driver output, the pull-down half is electrically coupled to receive the signal and the first control signal;
a fourth programmable driver leg having a pull-up half and a pull-down half, the pull-up half is electrically coupled between the supply voltage and the second driver output, the pull-up half is electrically coupled to receive the inversion of the signal and the second control signal, the pull-down half is electrically coupled between the internal ground and the second driver output, the pull-down half is electrically coupled to receive the signal and the second control signal;
the third programmable driver leg contributes to an output impedance of the second driver output when the first control signal is high and does not contribute to the output impedance of the second driver output when the first control signal is low; and
the fourth programmable driver leg contributes to the output impedance of the second driver output when the second control signal is high and does not contribute to the output impedance of the second driver output when the second control signal is low.

4. The programmable low power driver of claim 3 , the pull-down half of the third programmable driver leg further comprising:
a fifth termination resistor having a first end and a second end, the first end is electrically coupled to the internal ground;
a fifth logical element, having a first input, a second input, and an output, the first input is electrically coupled to receive the signal and the second input is electrically coupled to receive the second control signal; and
a fifth NMOS device having a source, a drain, and a gate, the gate is connected to the output of the fifth logical element, the drain is electrically coupled to the second driver output and the source is electrically coupled to the second end of the fifth termination resistor; and the pull-up half of the third programmable driver leg further comprising:
a sixth termination resistor having a first end and a second end, the first end is electrically coupled to the supply voltage;
a sixth logical element, having a first input, a second input, and an output, the first input is electrically coupled to receive the signal and the second input is electrically coupled to receive the first control signal; and
a sixth NMOS device having a source, a drain, and a gate, the gate is connected to the output of the sixth logical element, the source is electrically coupled to the second end of the sixth termination resistor, the drain is electrically coupled to the second driver output, the pull-down half of the fourth programmable driver leg further comprising:
a seventh termination resistor having a first end and a second end, the first end is electrically coupled to the internal ground;
a seventh logical element, having a first input, a second input, and an output, the first input is electrically coupled to receive the inverted signal and the second inp

Assignees

• Integrated Device Tech

Inventors

• Hsu John

Classifications

• H03K19/0005 Primary

  Modifications of input or output impedance · CPC title

• H03K19/01855

  synchronous, i.e. using clock signals · CPC title

• H03K19/018585

  programmable · CPC title

• H03K19/00361

  in field effect transistor circuits · CPC title