Method for controlling an integrated circuit

Patent metadata

Field	Value
Publication number	US-9479168-B2
Application number	US-201414225520-A
Country	US
Kind code	B2
Filing date	Mar 26, 2014
Priority date	Mar 26, 2013
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

First claim

Having described the invention, and a preferred embodiment thereof, what is claimed as new and secured by Letters Patent is:

1. A method for controlling an integrated circuit, said method comprising providing an integrated circuit that comprises logic cells, a clock-tree cell, and a semiconductor substrate, wherein said logic cells each comprise at least a first field-effect transistor and a second field-effect transistor, wherein said first field-effect transistor is a pMOS transistor, wherein said second field-effect transistor is an nMOS transistor, wherein said clock-tree cell comprises at least a third field-effect transistor and a fourth field-effect transistor, wherein said third field-effect transistor is a pMOS transistor, wherein said fourth field-effect transistor is an nMOS transistor, wherein said clock tree cell is configured to provide a clock signal to said logic cells, wherein said logic cells and said clock-tree cell are formed on said semiconductor substrate, wherein each of said field-effect transistors comprises a source, a drain, a conduction channel region, a gate stack, and a back gate, wherein said gate stack is disposed above said conduction channel region, wherein said back gate is disposed facing said gate stack on an opposite side of said conduction channel, and wherein a back gate potential difference of one of said field-effect transistors is defined as a difference between an electric potential applied to said source of said field-effect transistor less an electric potential applied to said back gate of said field-effect transistor, when said field-effect transistor is a pMOS transistor, and an electric potential applied to said back gate of said field-effect transistor less an electric potential applied to said source of said field-effect transistor, when said field-effect transistor is an nMOS transistor, said method further comprising applying a first back gate electric potential difference to a first field-effect transistor of a logic cell, applying a second back gate electric potential difference to a second field-effect transistor of said logic cell, and only one of applying a third back gate electric potential difference to said third field-effect transistor, wherein said third back gate potential difference is positive, wherein said third back gate potential difference has a value that is greater than said first back gate potential difference applied, which is applied concurrently, and applying a fourth back gate electric potential difference to said fourth field-effect transistor, wherein said fourth back gate potential difference is positive, wherein said fourth back gate potential difference has a value that is greater than said second back gate potential difference that is applied concurrently.

2. The method of claim 1 , wherein applying said first back gate electric potential difference to said first field-effect transistor of a logic cell comprises applying a potential difference having a positive value, and wherein applying said second back gate electric potential difference to said second field-effect transistor of said logic cell comprises applying a potential difference having a positive value.

3. The method of claim 1 , wherein providing an integrated circuit that comprises logic cells, a clock-tree cell, and a semiconductor substrate comprises providing an integrated circuit that further comprises at least one of a semiconductor well and a deep semiconductor well, wherein said at least one of a semiconductor well and a deep semiconductor well has a doping that is opposite to a doping of said semiconductor substrate, wherein said at least one of a semiconductor well and a deep semiconductor well is interposed between said back gate of said third field-effect transistor and said semiconductor substrate, and wherein said at least one of a semiconductor well and a deep semiconductor well is electrically insulated from said back gate of said first field-effect transistor by way of a p-n junction, wherein said p-n junction is a p-n junction that is able to be reverse biased during operation of said integrated circuit.

4. The method of claim 1 , wherein providing an integrated circuit that comprises logic cells, a clock-tree cell, and a semiconductor substrate comprises providing first, second, third and fourth field-effect transistors that are FDSOI technology transistors, each of which has a semiconductor back plane that is electrically insulated from a conduction channel thereof by a layer of electrically insulating material, said back plane forming a back gate of said field-effect transistor, wherein said first and third field-effect transistors include corresponding first and third semiconductor wells that have a doping of a first type and that extend under said back gates of said first and third field-effect transistors respectively, wherein said second and fourth field-effect transistors include corresponding second and fourth semiconductor wells having a doping of a second type that is opposite to said first type and that extend under said back gates of said second and fourth field-effect transistors respectively, providing said integrated circuit with a deep semiconductor well that is doped with a dopant of type opposite that of said semiconductor substrate, that extends under said wells, and that is in direct contact with said wells, and applying only one of said third back gate potential difference and said fourth back gate potential difference.

5. The method of claim 1 , wherein providing an integrated circuit that comprises logic cells, a clock-tree cell, and a semiconductor substrate comprises providing first, second, third, and fourth field-effect transistors that are bulk technology transistors, wherein said conduction channel is not electrically insulated from said back gate by a layer of electrically insulating material, wherein said first and third field-effect transistors include corresponding first and third semiconductor wells having n-type doping, wherein said second and fourth field-effect transistors include corresponding second and fourth semiconductor wells having p-type doping, wherein said wells form corresponding back gates of said field-effect transistors and wherein said wells are in direct electrical contact with said semiconductor substrate, and applying only said third back gate potential difference and not said fourth back gate potential difference.

6. The method of claim 1 , wherein providing an integrated circuit that comprises logic cells, a clock-tree cell, and a semiconductor substrate comprises providing first, second, third and fourth field-effect transistors that are bulk technology transistors, wherein said conduction channel is not electrically insulated from said back gate by a layer of electrically insulating material, said first and third field-effect transistors including corresponding first and third semiconductor wells having n-type doping, said second and fourth field-effect transistors including corresponding second and fourth semiconductor wells having p-type doping, providing a deep semiconductor well having doping of opposite type to said doping of said semiconductor substrate, said deep well extending at once under said first, second, third and fourth semiconductor wells so as to insulate said first, second, third and fourth semiconductor wells from said semiconductor substrate, and applying said fourth back gate potential difference but not said third back gate potential difference.

Assignees

• Commissariat L Energie Atomique Et Aux Energies Alternatives
• St Microelectronics Sa
• St Microelectronics Crolles 2 Sas

Inventors

• Giraud Bastien
• Abouzeid Fady
• Clerc Sylvain
• Noel Jean-Philippe
• Roche Philippe
• Thonnart Yvain

Classifications

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D84/907

  CMOS gate arrays · CPC title

• H10D84/859 Primary

  comprising both N-type and P-type wells, e.g. twin-tub · CPC title

• H01L27/1203

  Electricity · mapped topic

• H03K19/01855

  synchronous, i.e. using clock signals · CPC title