Integrated vacuum microelectronic structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9496392-B2
Application number	US-201514667215-A
Country	US
Kind code	B2
Filing date	Mar 24, 2015
Priority date	Mar 31, 2014
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

An integrated vacuum microelectronic structure is described as having a highly doped semiconductor substrate, a first insulating layer placed above said doped semiconductor substrate, a first conductive layer placed above said first insulating layer, a second insulating layer placed above said first conductive layer, a vacuum trench formed within said first and second insulating layers and extending to the highly doped semiconductor substrate, a second conductive layer placed above said vacuum trench and acting as a cathode, a third metal layer placed under said highly doped semiconductor substrate and acting as an anode, said second conductive layer is placed adjacent to the upper edge of said vacuum trench, the first conductive layer is separated from said vacuum trench by portions of said second insulating layer and is in electrical contact with said second conductive layer.

First claim

The invention claimed is:

1. An integrated vacuum microelectronic structure, comprising:
a highly doped semiconductor substrate;
a first insulating layer positioned on a first side of the highly doped semiconductor substrate;
a first conductive layer positioned on the first insulating layer;
a second insulating layer positioned on the first conductive layer;
a vacuum trench formed in the first and second insulating layers and extending to the highly doped semiconductor substrate;
a second conductive layer positioned over the vacuum trench and configured to be a cathode;
a third conductive layer positioned on a second side of the highly doped semiconductor substrate and configured to be an anode; and
a fourth conductive layer having a first portion positioned over the second conductive layer and a second portion extending from the second conductive layer through the second insulating layer to the first conductive layer, said second conductive layer is positioned adjacent to an upper edge of the vacuum trench, the first conductive layer is separated from the vacuum trench by portions of the second insulating layer.

2. The integrated vacuum microelectronic structure according to claim 1 wherein said vacuum trench has a width, the second conductive layer being suspended over said vacuum trench, across the width.

3. The integrated vacuum microelectronic structure according to claim 1 wherein said vacuum trench includes a third insulating layer on sidewalls of the vacuum trench.

4. The integrated vacuum microelectronic structure according to claim 1 wherein said first conductive layer is made of doped polysilicon, having a dopant concentration higher than 10 18 atoms/cm 3 .

5. The integrated vacuum microelectronic structure according to claim 1 wherein said vacuum trench has a width in the range of 0.3 micrometers and 0.6 micrometers.

6. The integrated vacuum microelectronic structure according to claim 1 wherein said first conductive layer has a ring shape structure, said vacuum trench being formed inside a hole of said ring shape structure.

7. The integrated vacuum microelectronic structure according to claim 6 wherein a depth of the vacuum trench depends on a thickness of the first and the second insulating layers and a threshold voltage of the integrated vacuum microelectronic structure depends on a diameter of the ring shape structure.

8. The integrated vacuum microelectronic structure according to claim 6 wherein said ring shape structure is a toroid shape structure.

9. The integrated vacuum microelectronic structure according to claim 6 wherein said ring shape structure has an internal diameter in the range of 1 micrometer and 4 micrometers.

10. An integrated device, comprising:
a plurality of vacuum microelectronic structures arranged in parallel to each other, each microelectronic structure including:
a highly doped semiconductor substrate;
a first insulating layer positioned on a first side of the highly doped semiconductor substrate;
a first conductive layer positioned on the first insulating layer;
a second insulating layer positioned on the first conductive layer;
a vacuum trench formed in the first and second insulating layers and extending to the highly doped semiconductor substrate;
a second conductive layer positioned over the vacuum trench and configured to be a cathode;
a third insulating layer positioned over the second insulating layer and the second conductive layer, the third insulating layer having an opening exposing the second conductive layer;
a third conductive layer formed in the opening; and
a fourth conductive layer positioned on a second side of the highly doped semiconductor substrate and configured to be an anode, said second conductive layer is positioned adjacent to an upper edge of the vacuum trench, the first conductive layer is separated from the vacuum trench by portions of the second insulating layer and is in electrical contact with the second conductive layer.

11. The integrated device of claim 10 wherein the fourth conductive layer is formed as a plurality of interlocking ring structures, each vacuum trench being formed in a hole in a respective one of the plurality of interlocking ring structures.

12. A device, comprising:
a substrate;
a first conductive structure formed on a first surface of the substrate;
a vacuum trench formed between portions of the first conductive structure, a first end of the vacuum trench in contact with the substrate;
a second conductive structure on a second end of the vacuum trench, the second conductive structure being configured to seal the vacuum trench, the second conductive structure being a cathode;
a third conductive structure that electrically couples the first conductive structure to the second conductive structure, the third conductive structure having a first portion separated from the second end of the vacuum trench by the second conductive structure and a second portion lateral to sidewalls of the vacuum trench; and
a fourth conductive structure on a second surface of the substrate, the fourth conductive structure being an anode.

13. The device of claim 12 , further comprising a first insulating layer between the substrate and the first conductive structure, the vacuum trench extending through the first insulating layer and a second insulating layer on top and side surfaces of the first conductive structure, the second insulating layer separating the vacuum trench from the first conductive structure.

14. The device of claim 13 wherein the first conductive structure includes a central portion that extends into the vacuum trench and distal portion that is in contact with the second insulating layer.

15. A device, comprising:
a substrate including:
a first surface; and
a second surface opposite to the first surface;

an anode on the first surface of the substrate;
a first insulating layer on the second surface of the substrate;
a first conductive layer on the first insulating layer;
a second insulating layer on the first insulating layer and the first conductive layer;
a trench formed in the first insulating layer and the second insulating layer, the trench having an opening adjacent to the second insulating layer;
a cathode positioned on the opening of the trench; and
a second conductive layer including:
a first portion over the cathode and the second insulating layer; and
a second portion that extends through the second insulating layer and contacts the first conductive layer, the second portion and the first conductive layer being separated from the sidewalls of the trench by the second insulating layer.

16. The device of claim 15 , further comprising a third insulating layer over the cathode and the second insulating layer, the third insulating layer having an opening that exposes the cathode.

17. The device of claim 16 , wherein the second conductive layer is formed over the third insulating layer and in the opening of the third insulating layer.

18. The device of claim 15 , wherein the first portion extends in a first direction that is substantially parallel to the second surface of the substrate, and the second portion extends in a second direction that is substantially perpendicular to the second surface of the substrate.

19. The device of claim 15 , further comprising a third insulating layer on sidewalls of the trench.

Assignees

• St Microelectronics Srl

Inventors

• Patti Davide Giuseppe
• Grasso Gianleonardo

Classifications

• H01J21/105

  with microengineered cathode and control electrodes, e.g. Spindt-type · CPC title

• H01J1/3044

  Point emitters · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D62/81

  of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title