Nano vacuum gap device with a gate-all-around cathode

Patent metadata

Field	Value
Publication number	US-9953796-B2
Application number	US-201615098108-A
Country	US
Kind code	B2
Filing date	Apr 13, 2016
Priority date	Apr 14, 2015
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A semiconductor power handling device, includes a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode by a nano-vacuum gap. An array of semiconductor power handling devices, each comprising a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode pillar by a nano-vacuum gap. The semiconductor power handling devices can be arranged as rows and columns and can be interconnected to meet the requirements of various applications. The array of power handling devices can be fabricated on a single substrate.

First claim

The invention claimed is:

1. A semiconductor power handling device, comprising:
a cathode pillar;
a gate surrounding the cathode pillar; and
an anode spaced from the cathode pillar by a nano-vacuum gap.

2. The device of claim 1 wherein the cathode pillar is a prism of any cross section.

3. The device of claim 1 wherein the cathode pillar has a width of between 100 nm to 1 μm.

4. The device of claim 1 wherein the cathode pillar has a height of between 10 nm and 10 μm.

5. The device of claim 1 wherein the cathode pillar is a pyramid.

6. The device of claim 5 wherein the cross-section of the pyramid is a circle.

7. The device of claim 5 wherein the cross-section of the pyramid is any polygon.

8. The device of claim 1 wherein the cathode pillar has a varying cross-section from pillar bottom to pillar top.

9. The device of claim 1 wherein said nano-vacuum gap has a width of between 1 nm and 1 μm.

10. The device of claim 1 wherein the gate comprises: a dielectric layer on the side of and surrounding the cathode pillar; and a gate layer on the side of and surrounding the dielectric layer.

11. The device of claim 1 wherein the vacuum level within the nano-vacuum gap is between 1 microtorr and 10 Torr.

12. The device of claim 1 wherein the device is fabricated monolithically on a semiconductor substrate.

13. The device of claim 12 wherein the semiconductor substrate is selected from a group consisting of Si, GaN, diamond, and SiC.

14. The device of claim 1 wherein the anode material is selected from a group consisting of Si, GaN, diamond, and SiC.

15. The device of claim 1 replicated in an array on a substrate with each device comprising a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode by a nano-vacuum gap wherein the devices are interconnected.

16. An array of semiconductor power handling devices, each comprising a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode pillar by a nano-vacuum gap.

17. The array of devices of claim 16 , wherein the array comprises the power handling devices arranged in an array of adjacent rows and columns.

18. The array of claim 17 wherein anodes of adjacent power handling devices in a row are interconnected.

19. The array of claim 17 wherein gates of adjacent power handling devices in a column are interconnected.

20. The array of claim 17 wherein the areal density of power handling devices in the array is greater than 10 5 device/mm 2 .

21. The array of claim 17 wherein the linear density of power handling devices in the array is greater than 100 device/mm.

22. A method for fabricating a power handling device on a semiconductor substrate, comprising:
fabricating a cathode pillar;
fabricating a gate surrounding the cathode pillar; and
fabricating an anode spaced from the cathode pillar by a nano-vacuum gap.

23. The method of claim 22 wherein fabricating the cathode pillar comprises:
fabricating a pillar on the semiconductor substrate using a lithography/etch process;
forming a substrate oxidation layer atop the substrate and pillar; and refining the pillar using a substrate oxidation/etch process to form the pillar having a size less than one micron.

24. The method of claim 22 comprising refining the cathode pillar to have a circular cross-section.

25. The method of claim 22 comprising refining the cathode pillar to have a polygon cross-section.

26. The method of claim 22 wherein fabricating a gate surrounding the cathode pillar comprises:
forming a dielectric layer surrounding the cathode pillar having a thickness of less than 100 nm; and
depositing a metal gate layer over the dielectric layer and surrounding the cathode pillar using atomic layer deposition, and having a thickness between 1 nm to 5 microns.

27. The method of claim 26 further comprising after fabricating the gate surrounding the cathode pillar, implanting a cathode contact beneath the dielectric layer in the substrate using an ion implantation process.

28. The method of claim 26 further comprising after fabricating the gate surrounding the cathode pillar:
filling depressions in the substrate with a filler material; and
planarizing the substrate using a chemical-mechanical planarization process.

29. The method of claim 26 wherein fabricating an anode separated from the pillar by a nano-vacuum gap comprises:
depositing a sacrificial layer on the surface of the substrate; depositing a covering layer on the surface of the sacrificial layer; drilling a hole through the covering layer to the sacrificial layer;
removing a portion of the sacrificial layer using an etch process to form a nano-vacuum gap between the cathode and anode.

30. A method for using a semiconductor power handing device having a cathode comprising a cathode pillar and a cathode contact, a gate surrounding the cathode pillar and an anode spaced from the cathode pillar by a nano-vacuum gap and connected to an anode contact, comprising:
coupling a power voltage supply and a load between the cathode contact and the anode contact;
coupling a control voltage supply between the cathode contact and the gate; and
varying the voltage of the control voltage supply to vary the current through the load.

31. The device of claim 1 wherein said nano-vacuum gap has a width that is less than the electron mean free path in the environment surrounding said nano-vacuum gap; and wherein the vacuum pressure in said nano-vacuum gap is comprised between 1 microtorr and atmospheric pressure.

Assignees

• Hrl Lab Llc

Inventors

• Huang Biqin
• Roper Christopher S
• Hussain Tahir

Classifications

• H01J21/10 Primary

  with one or more immovable internal control electrodes, e.g. triode, pentode, octode · CPC title

• H01J1/308 Primary

  Semiconductor cathodes, e.g. cathodes with PN junction layers · CPC title

• H01J21/105

  with microengineered cathode and control electrodes, e.g. Spindt-type · CPC title

• H01J9/025

  of field emission cathodes · CPC title

• H01J1/304

  Field-emissive cathodes · CPC title