Negative capacitance logic device, clock generator including the same and method of operating clock generator

Patent metadata

Field	Value
Publication number	US-9484924-B2
Application number	US-201514614884-A
Country	US
Kind code	B2
Filing date	Feb 5, 2015
Priority date	Jan 19, 2015
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A negative capacitance logic device includes a first field effect transistor (FET) and a second FET. The first FET is coupled between a power supply voltage and an output node, and the first FET includes a ferroelectric having a negative capacitance. The second FET is coupled between the output node and a ground voltage, and the second FET includes a ferroelectric having a negative capacitance. The negative capacitance logic differentiates an input voltage applied to an input node to provide an output voltage at the output node.

First claim

What is claimed is:

1. A negative capacitance logic device comprising:
a first field effect transistor (FET) coupled between a power supply voltage and an output node, the first FET including a ferroelectric having a negative capacitance; and
a second (FET) coupled between the output node and a ground voltage, the second FET including a ferroelectric having a negative capacitance,
wherein the negative capacitance logic is configured to differentiate an input voltage applied to an input node to provide an output voltage at the output node,
wherein the first FET includes a p-channel FET that has a source region coupled to the power supply voltage, a gate electrode coupled to the input node and a drain region coupled to the output node,
wherein the second FET includes an n-channel FET that has a drain region coupled to the power supply voltage, a gate electrode coupled to the input node and a source region coupled to the output node,
wherein each of the first FET and the second FET includes a dielectric layer including at least the ferroelectric,
wherein the dielectric layer is formed between the gate electrode and an channel region that is formed between the drain region and the source region in a substrate, and
wherein the dielectric layer further comprises a gate oxide layer and a metal layer which are sequentially interposed between the channel region and the ferroelectric.

2. The negative capacitance logic device of claim 1 , wherein each of the first FET and the second FET has a hysteresis characteristic in response to a change of the input voltage applied to the gate electrode.

3. A negative capacitance logic device comprising:
a first field effect transistor (FET) coupled between a power supply voltage and an output node, the first FET including a ferroelectric having a negative capacitance; and
a second (FET) coupled between the output node and a ground voltage, the second FET including a ferroelectric having a negative capacitance,
wherein the negative capacitance logic is configured to differentiate an input voltage applied to an input node to provide an output voltage at the output node,
wherein the first FET includes a p-channel FET that has a source region coupled to the power supply voltage, a gate electrode coupled to the input node and a drain region coupled to the output node,
wherein the second FET includes an n-channel FET that has a drain region coupled to the power supply voltage, a gate electrode coupled to the input node and a source region coupled to the output node,
wherein the first FET and the second FET includes a dielectric layer including at least the ferroelectric,
wherein the dielectric layer is formed between the gate electrode and an channel region that is formed between the drain region and the source region in a substrate, and
wherein the dielectric layer further comprises a gate oxide layer which is interposed between the channel region and the ferroelectric.

4. The negative capacitance logic device of claim 1 , wherein the negative capacitance logic device operates as a Schmitt-trigger inverter.

5. A clock generator comprising:
a spin torque oscillator configured to generate an oscillating signal having a first frequency in response to an applied direct current; and
a negative capacitance logic device configured to generate a clock signal toggling with the first frequency, in response to the oscillating signal,
wherein the spin toque oscillator comprises:
a first free layer;
a nonmagnetic layer disposed on the first free layer; and
a second free layer disposed on the nonmagnetic layer, the second free layer corresponding to the first free layer,
wherein the first free layer and the second free layer have perpendicular magnetic anisotropy or in-plane magnetic anisotropy.

6. The clock generator of claim 5 , wherein the nonmagnetic layer is one of a conductive layer and an insulating layer and
wherein the first free layer and the second free layer have the same thickness.

7. The clock generator of claim 5 , wherein the spin toque oscillator includes a magnetic tunnel junction (MTJ) structure, and wherein the MTJ structure comprises:
a pinned layer;
a tunnel layer disposed on the pinned layer; and
a free layer disposed on the tunnel layer.

8. The clock generator of claim 5 , wherein the spin toque oscillator includes a giant magneto resistance (GMR) structure, and wherein the GMR structure comprises:
a pinned layer;
a nonmagnetic layer disposed on the pinned layer; and
a free layer disposed in the nonmagnetic layer.

9. The clock generator of claim 5 , wherein the negative capacitance logic device comprises:
a first field effect transistor (FET) coupled between a power supply voltage and an output node, the first FET including a ferroelectric having a negative capacitance; and
a second (FET) coupled between the output node and a ground voltage, the second FET including a ferroelectric having a negative capacitance, and
wherein the negative capacitance logic is configured to differentiate the oscillating signal applied to an input node coupled to the spin torque oscillator to provide the clock signal at the output node.

10. The clock generator of claim 9 , wherein the first FET includes a p-channel FET that has a source region coupled to the power supply voltage, a gate electrode coupled to the input node and a drain region coupled to the output node, and
wherein the second FET includes an n-channel FET that has a drain region coupled to the power supply voltage, a gate electrode coupled to the input node and a source region coupled to the output node.

11. The clock generator of claim 10 , wherein each of the first FET and the second FET includes a dielectric layer including at least the ferroelectric, and
wherein the dielectric layer is formed between the gate electrode and an channel region that is formed between the drain region and the source region in a substrate.

Assignees

• Shin Min Cheol
• Lee Jae Hyun
• Kang Doo Hyung
• Seo Jun Beom
• Jeong Woo Jin
• Korea Advanced Inst Sci & Tech

Inventors

• Shin Min Cheol
• Lee Jae Hyun
• Kang Doo Hyung
• Seo Jun Beom
• Jeong Woo Jin

Classifications

• H10D48/385

  Devices using spin-polarised carriers · CPC title

• H01L29/66984

  Electricity · mapped topic

• H03B15/006

  using spin transfer effects or giant magnetoresistance · CPC title

• H01L43/10

  Electricity · mapped topic

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title