Clocked all-spin logic circuit

Patent metadata

Field	Value
Publication number	US-9712171-B2
Application number	US-201314129527-A
Country	US
Kind code	B2
Filing date	Sep 11, 2013
Priority date	Sep 11, 2013
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Described is a latch comprising: a first all-spin logic (ASL) device; a second ASL device coupled to the first ASL device, the second ASL device controllable by a clock signal; and a third ASL device coupled to the second ASL device, wherein the first and third ASL devices have respective magnets coupled to a power supply terminal. Described is a flip-flop which comprises: a first ASL device; a second ASL device coupled to the first ASL device, the second ASL device controllable by a first clock signal; a third ASL device coupled to the second ASL device, the third ASL device controllable by a second clock signal, the second clock signal being out of phase relative to the first clock signal; and a fourth ASL device coupled to the third ASL device, wherein the first and fourth ASL devices have respective magnets coupled to a power supply terminal.

First claim

We claim:

1. An apparatus comprising:
a first ferromagnet;
a second ferromagnet coupled to the first ferromagnet, the second ferromagnet is controlled by a clock signal during operation; and
a third ferromagnet coupled to the second ferromagnet, wherein the first and third ferromagnets have respective magnets coupled to a power supply terminal.

2. The apparatus of claim 1 , wherein each of the first, second, and third ferromagents form a first, second, and third all-spin logic (ASL) devices respectively, each of which includes:
a magnet with a first terminal, the magnet extending in a first direction;
a non-magnet with a second terminal, the non-magnet extending in a second direction different from the first direction; and
a non-conductor coupled to the magnet, the non-conductor extending in the second direction to isolate a first portion of a non-magnet interconnect from a second portion of the non-magnet interconnect, the second portion coupled to the magnet and the non-magnet, the non-magnet interconnect extending in the first direction.

3. The apparatus of claim 2 , wherein the first terminal is coupled to a power supply terminal for the first ASL device.

4. The apparatus of claim 2 , wherein the first terminal is coupled to the clock signal for the second ASL device.

5. The apparatus of claim 2 , wherein the first terminal is coupled to a power supply terminal for the third ASL device.

6. The apparatus of claim 2 , wherein the second terminal is coupled to ground.

7. The apparatus of claim 2 , wherein the first terminal for each of the ASL devices is independently controllable to be coupled to a positive power supply, a negative power supply, or a floating node.

8. The apparatus of claim 7 further comprises a clock gating control circuit to provide a control signal for independently controlling coupling of the first terminal to a positive power supply, a negative power supply, or a floating node.

9. The apparatus of claim 1 , wherein the power supply terminal is coupled to at least one of:
a positive power supply;
a negative power supply; or
a floating node.

10. An apparatus comprising:
a first ferromagnet;
a second ferromagnet coupled to the first ferromagnet, the second ferromagnet is controlled by a first clock signal during operation;
a third ferromagnet coupled to the second ferromagnet, the third ferromagnet is controlled by a second clock signal during operation, the second clock signal being out of phase relative to the first clock signal; and
a fourth ferromagnet coupled to the third ferromagnet, wherein the first and fourth ferromagnets have respective magnets coupled to a power supply terminal.

11. The apparatus of claim 10 , wherein each of the first, second, third, and fourth ferromagnet form a first, second, third, and fourth all-spin logic (ASL) devices respectively, each of which include:
a magnet with a first terminal, the magnet extending in a first direction;
a non-magnet with a second terminal, the non-magnet extending in a second direction different from the first direction; and
a non-conductor coupled to the magnet, the non-conductor extending in the second direction to isolate a first portion of a non-magnet interconnect from a second portion of the non-magnet interconnect, the second portion coupled to the magnet and the non-magnet, the non-magnet interconnect extending in the first direction.

12. The apparatus of claim 11 , wherein the first terminal is coupled to a power supply terminal for the first ASL device.

13. The apparatus of claim 11 , wherein the first terminal is coupled to the first clock signal for the second ASL device.

14. The apparatus of claim 11 , wherein the first terminal is coupled to the second clock signal for the third ASL device.

15. The apparatus of claim 11 , wherein the first terminal is coupled to a power supply terminal for the fourth ASL device.

16. The apparatus of claim 11 , wherein the second terminal is coupled to ground.

17. The apparatus of claim 11 , wherein the first terminal for each of the ASL devices is independently controllable to be coupled to a positive power supply, a negative power supply, or a floating node.

18. The apparatus of claim 17 further comprises a clock gating control circuit to provide a control signal for independently controlling coupling of the first terminal to a positive power supply, a negative power supply, or a floating node.

19. The apparatus of claim 10 , wherein the power supply terminal is coupled to at least one of:
a positive power supply;
a negative power supply; or
a floating node.

20. A system comprising:
a memory;
a processor coupled to the memory, the processor having a latch which includes:
a first ferromagnet;
a second ferromagnet coupled to the first ferromagnet, the second ferromagnet is controlled by a clock signal during operation; and
a third ferromagnet coupled to the second ferromagnet, wherein the first and third ferromagnets have respective magnets coupled to a power supply terminal; and

a wireless interface for allowing the processor to communicate with another device.

21. The system of claim 20 further comprises a display unit.

Assignees

• Nikonov Dmitri E
• Manipatruni Sasikanth
• Young Ian A
• Calayir Vehbi
• Intel Corp

Inventors

• Nikonov Dmitri E
• Manipatruni Sasikanth
• Young Ian A
• Calayir Vehbi

Classifications

• B82Y25/00

  Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/16 Primary

  using saturable magnetic devices · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H03K3/45 Primary

  by the use, as active elements, of non-linear magnetic or dielectric devices · CPC title