Magnetic memory and semiconductor-integrated-circuit

Patent metadata

Field	Value
Publication number	US-9570137-B2
Application number	US-201615067586-A
Country	US
Kind code	B2
Filing date	Mar 11, 2016
Priority date	Sep 24, 2013
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A magnetic memory includes a magnetoresistive device and a load resistance unit. The magnetoresistive device has a first resistance state and a second resistance state and includes a first ferromagnetic layer and a second ferromagnetic layer. The load resistance unit is electrically connected to the magnetoresistive device. The load resistance unit is in a first state and a second state. Differential resistance of the load resistance unit at the second state is lower than differential resistance of the load resistance unit at the first state.

First claim

What is claimed is:

1. A magnetic memory, comprising:
a magnetoresistive device having a first resistance state and a second resistance state and including a first ferromagnetic layer and a second ferromagnetic layer, a direction of magnetization of the first ferromagnetic layer being changeable, a direction of magnetization of the second ferromagnetic layer being changeable, resistance between the first ferromagnetic layer and the second ferromagnetic layer being higher in the second resistance state than in the first resistance state;
a load resistance unit electrically connected to the magnetoresistive device, the load resistance unit having a first state and a second state, differential resistance of the load resistance unit at the second state being lower than differential resistance of the load resistance unit at the first state; and
a controller switching the magnetoresistive device to the first resistance state by current flowing in a first direction between the first ferromagnetic layer and the second ferromagnetic layer with the load resistance unit being set to the first state, the controller switching the magnetoresistive device to the second resistance state by current flowing in the first direction between the first ferromagnetic layer and the second ferromagnetic layer with the load resistance unit being set to the second state.

2. The memory according to claim 1 , wherein
first critical current where the magnetoresistive device changes from the second resistance state to the first resistance state is smaller than second critical current where the magnetoresistive device changes from the first resistance state to the second resistance state,
the current flowing in the magnetoresistive device in the first resistance state after the magnetoresistive device changes from the second resistance state to the first resistance state by the current flowing in the first direction is smaller than the second critical current, and
the current flowing in the magnetoresistive device in the second resistance state after the magnetoresistive device changes from the first resistance state to the second resistance state by the current flowing in the first direction is smaller than the first critical current.

3. The memory according to claim 2 , wherein
the value of differential resistance RL 1 is greater than (Ic 1 ×RS 2 −Ic 2 ×RS 1 )/(Ic 2 −Ic 1 ), and
the value of differential resistance RL 2 is less than (Ic 1 ×RS 2 −Ic 2 ×RS 1 )/(Ic 2 −Ic 1 ), where
Ic 1 is the first critical current,
Ic 2 is the second critical current,
RS 1 is a resistance value of the magnetoresistive device when current near the second critical current flows in the magnetoresistive device in the first resistance state,
RS 2 is a resistance value of the magnetoresistive device when current near the first critical current flows in the magnetoresistive device in the second resistance state,
RL 1 is differential resistance of the load resistance unit of the first state, and
RL 2 is differential resistance of the load resistance unit of the second state.

4. The memory according to claim 1 , wherein the load resistance unit includes:
a first resistance device;
a second resistance device, differential resistance of the second resistance device being lower than differential resistance of the first resistance device; and
a switching unit switching the load resistance unit to the first state by electrically connecting the first resistance device to the magnetoresistive device, the switching unit switching the load resistance unit to the second state by electrically connecting the second resistance device to the magnetoresistive device.

5. The memory according to claim 4 , wherein
the load resistance unit includes:
a first terminal set to a first electric potential; and
a second terminal set to a second electric potential,

the absolute value of the first electric potential is higher than the absolute value of the second electric potential,
the first resistance device is electrically connected to the first terminal, and
the second resistance device is electrically connected to the second terminal.

6. The memory according to claim 4 , wherein
the load resistance unit includes:
a first terminal set to a first electric potential; and
a second terminal set to a second electric potential,

the absolute value of the first electric potential is higher than the absolute value of the second electric potential,
the first resistance device and the second resistance device are connected in parallel with the magnetoresistive device via the switching unit, and
the load resistance unit is switched to the first state when the first terminal and the first resistance device are connected to the magnetoresistive device, and the load resistance unit is switched to the second state when the second terminal and the second resistance device are connected to the magnetoresistive device.

7. The memory according to claim 4 , wherein
the load resistance unit includes:
a first terminal set to a first electric potential; and
a second terminal set to a second electric potential,

the absolute value of the first electric potential is higher than the absolute value of the second electric potential,
the first resistance device is connected in series between the first terminal and the magnetoresistive device via the switching unit,
the second resistance device is connected in parallel with the magnetoresistive device via the switching unit, and
the load resistance unit is switched to the first state when the first terminal and the first resistance device are connected to the magnetoresistive device, and the load resistance unit is switched to the second state when the second terminal and the second resistance device are connected to the magnetoresistive device.

8. The memory according to claim 4 , wherein
the load resistance unit includes:
a first terminal set to a first electric potential; and
a second terminal set to a second electric potential,

the absolute value of the first electric potential is higher than the absolute value of the second electric potential,
the first resistance device is connected in parallel with the magnetoresistive device via the switching unit,
the second resistance device is connected in series between the second terminal and the magnetoresistive device via the switching unit, and
the load resistance unit is switched to the first state when the first terminal and the first resistance device are connected to the magnetoresistive device, and the load resistance unit is switched to the second state when the second terminal and the second resistance device are connected to the magnetoresistive device.

9. The memory according to claim 4 , wherein
the load resistance unit includes a first terminal set to a first electric potential,
the first resistance device and the second resistance device are connected in parallel with the magnetoresistive device via the switching unit, and
the load resistance unit is switched to the first state when the first terminal and the first resistance device are connected to the magnetoresistive device, and the load resistance unit is switched to the second state when the first terminal and the second resistance device are connected to the magnetoresistive device.

10. The memory according to claim 1 , wherein the load resistance unit includes a MOSFET, a gate terminal and a drain terminal of the MOSFET being connected to each other.

11. The memory according to claim 10 , comprising a pair of power supply terminals,
the load resistance unit including a semiconductor device and a switching device,
the magnetoresistive device being provided bet

Assignees

• Toshiba Kk

Inventors

• Sugiyama Hideyuki
• Tanamoto Tetsufumi
• Ishikawa Mizue
• Inokuchi Tomoaki
• Saito Yoshiaki

Classifications

• G11C11/165 Primary

  Auxiliary circuits · CPC title

• H01L27/228

  Electricity · mapped topic

• H03K19/16

  using saturable magnetic devices · CPC title

• H01L43/08

  Electricity · mapped topic

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title