Testing system for serial interface

Patent metadata

Field	Value
Publication number	US-9360524-B2
Application number	US-201414305188-A
Country	US
Kind code	B2
Filing date	Jun 16, 2014
Priority date	Jun 19, 2013
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A testing system includes a circuit board, and an inserting unit. The circuit board includes a first serial interface and a serial chip connected to the first serial interface. The first serial interface connects a second serial interface of a motherboard to receive a first signal of the second serial interface. The inserting unit includes a first plug connected to a pin Transmit Data of the first serial interface. The first plug connects a testing device. When the first signal is transmitted to the first serial interface by the second serial interface, the serial chip receives the first signal and sends the first signal back to the first serial interface. The first plug sends a second signal of the pin Transmit Data to the testing device to be tested.

First claim

What is claimed is:

1. A testing system comprising:
a circuit board comprising a first serial interface and a serial chip connected to the first serial interface; the first serial interface is configured to connect a second serial interface of a motherboard to receive a first signal of the second serial interface; and
an inserting unit comprising a first plug connected to a pin Transmit Data of the first serial interface; the first plug is configured to connect a testing device;
wherein when the first signal is transmitted to the first serial interface by the second serial interface, the serial chip is configured to receive the first signal sent by the first serial interface and send the first signal back to the first serial interface, and the first plug is configured to send a second signal of the pin Transmit Data to the testing device to be tested.

2. The testing system of claim 1 , wherein the inserting unit further comprises a second plug connected to a pin Data Terminal Ready of the first serial interface, and the second plug is configured to connect the testing device for sending a third signal of the pin Data Terminal Ready to the testing device.

3. The testing system of claim 2 , wherein the inserting unit further comprises a third plug connected to a pin Request To Send of the first serial interface, and the third plug is configured to connect the testing device for sending a fourth signal of the pin Request To Send to the testing device.

4. The testing system of claim 3 , wherein the pin Transmit Data, the pin Data Terminal Ready, and the Request To Send of the first serial interface are connected to a first pin Receive Input, a second pin Receive Input, and a third pin Receive Input of the serial chip, respectively.

5. The testing system of claim 4 , wherein the first pin Receive Input, the second pin Receive Input, and the third pin Receive Input of the serial chip are connected to the first plug, the second plug and the third plug, respectively.

6. The testing system of claim 1 , wherein a first Receive Output, a second Receive Output, a third Receive Output are connected to a fifth Data Input, a first Data Input, and a third Data Input of the serial chip, and a fourth Data Input of the serial chip is connected to a pin DIN1 of the serial chip.

7. The testing system of claim 1 , wherein a pin Carrier Detect, a pin Ring Indicator, a pin Clear To Send, a pin Data Set Ready, and a pin Receive Data of the first serial interface are connected to a first pin Data Output, a second pin Data Output, a third pin Data Output, a fourth pin Data Output, and a fifth pin Data Output of the serial chip, respectively.

8. The testing system of claim 1 , wherein a positive pole of a first capacitor is connected to a first capacitor positive terminal of the serial chip, a negative pole of the first capacitor is connected to the first capacitor positive terminal of the serial chip, a positive pole of a second capacitor is connected to a second capacitor positive terminal of the serial chip, and a negative pole of the second capacitor is connected to the second capacitor positive terminal of the serial chip.

9. The testing system of claim 1 , wherein a positive pole of a third capacitor is connected to a voltage positive terminal of the serial chip, a negative pole of the third capacitor is grounded, a positive pole of a fourth capacitor is connected to a voltage negative terminal of the serial chip, and a negative pole of the fourth capacitor is grounded.

10. The testing system of claim 1 , wherein the serial chip is MAX3238.

11. A testing system comprising:
a circuit board comprising a first serial interface and a serial chip connected to the first serial interface; the first serial interface is configured to connect a second serial interface of a motherboard to receive a first signal of the second serial interface; and
an inserting unit comprising a first plug connected to a pin Transmit Data of the first serial interface and connected to a first pin Receive Input of the serial chip; the first plug is configured to connect a testing device;
wherein the first signal is transmitted to the serial chip via the first serial interface, and the first signal received by the serial chip is sent back to the first serial interface via the serial chip, and the first plug is configured to send a second signal of the pin Transmit Data to the testing device to be tested.

12. The testing system of claim 11 , wherein the inserting unit further comprises a second plug connected to a pin Data Terminal Ready of the first serial interface, and the second plug is configured to connect the testing device for sending a third signal of the pin Data Terminal Ready to the testing device.

13. The testing system of claim 12 , wherein the inserting unit further comprises a third plug connected to a pin Request To Send of the first serial interface, and the third plug is configured to connect the testing device for sending a fourth signal of the pin Request To Send to the testing device.

14. The testing system of claim 13 , wherein the pin Transmit Data is connected to the first pin Receive Input of the serial chip, and the pin Data Terminal Ready and the Request To Send of the first serial interface are connected to a second pin Receive Input and a third pin Receive Input of the serial chip, respectively.

15. The testing system of claim 14 , wherein the first pin Receive Input, the second pin Receive Input, and the third pin Receive Input of the serial chip are connected to the first plug, the second plug and the third plug, respectively.

16. The testing system of claim 11 , wherein a first Receive Output, a second Receive Output, a third Receive Output are connected to a fifth Data Input, a first Data Input, and a third Data Input of the serial chip, and a fourth Data Input of the serial chip is connected to a pin DIN1 of the serial chip.

17. The testing system of claim 11 , wherein a pin Carrier Detect, a pin Ring Indicator, a pin Clear To Send, a pin Data Set Ready, and a pin Receive Data of the first serial interface are connected to a first pin Data Output, a second pin Data Output, a third pin Data Output, a fourth pin Data Output, and a fifth pin Data Output of the serial chip, respectively.

18. The testing system of claim 11 , wherein a positive pole of a first capacitor is connected to a first capacitor positive terminal of the serial chip, a negative pole of the first capacitor is connected to the first capacitor positive terminal of the serial chip, a positive pole of a second capacitor is connected to a second capacitor positive terminal of the serial chip, and a negative pole of the second capacitor is connected to the second capacitor positive terminal of the serial chip.

19. The testing system of claim 11 , wherein a positive pole of a third capacitor is connected to a voltage positive terminal of the serial chip, a negative pole of the third capacitor is grounded, a positive pole of a fourth capacitor is connected to a voltage negative terminal of the serial chip, and a negative pole of the fourth capacitor is grounded.

20. The testing system of claim 11 , wherein the serial chip is MAX3238.

Assignees

• Scienbizip Consulting Shenzhen Co Ltd
• Scienbizip Consulting Shenzhen Co Ltd

Inventors

• Shu Shou-Li
• Huang Wen-Min

Classifications

• G01R31/31905 Primary

  Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture · CPC title

• G01R31/3187

  Built-in tests · CPC title