Integrated circuit testing interface on automatic test equipment

Patent metadata

Field	Value
Publication number	US-9435863-B2
Application number	US-201414492067-A
Country	US
Kind code	B2
Filing date	Sep 21, 2014
Priority date	Jan 24, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

An integrated circuit (IC) testing interface capable of upgrading an automatic test equipment (ATE) for testing a semiconductor device includes at least one pin for receiving or transmitting at least a test signal to a tester of the automatic test equipment, a plurality of digitizers coupled to the at least one pin for generating a digital signal, a processing means coupled to the plurality of digitizers for processing the digital signal, and a connection unit for connecting the processing means with a computing device for transmitting an output signal from the processing means to the computing device, where the IC testing interface is disposed between the tester and a prober of the automatic test equipment.

First claim

What is claimed is:

1. An integrated circuit (IC) testing interface, capable of upgrading an automatic test equipment (ATE) for testing a semiconductor device, the IC testing interface comprising:
at least one pin, configured for receiving or transmitting at least one test signal to a tester of the automatic test equipment;
a plurality of digitizers, coupled to the at least one pin for generating a digital signal;
a processing means, coupled to the plurality of digitizers for processing the digital signal; and
a connection unit, configured for connecting the processing means with a computing device for transmitting an output signal from the processing means to the computing device;
wherein the IC testing interface is disposed between the tester and a prober of the automatic test equipment;
wherein the at least one pin comprises:
a first pin, configured for transmitting a first test signal of the at least one test signal to the tester of the ATE, wherein the first test signal comprises an enabling signal for reading or writing a testing datum;
a second pin, configured for transmitting a second test signal of the at least one test signal to the tester of the ATE, wherein the second test signal comprises a sampling signal for determining a sampling number of the semiconductor device; and
a third pin, configured for transmitting a third test signal of the at least one test signal to the tester of the ATE, wherein the third test signal comprises a testing result.

2. The IC testing interface of claim 1 , wherein the processing means converts or sorts the digital signal, calibrates an offset of the digital signal, or takes an arithmetic operation on the digital signal.

3. The IC testing interface of claim 1 , wherein the IC testing interface integrates a probe interface board, a load board, or a probe board so as to be installed in the ATE.

4. The IC testing interface of claim 1 , wherein each of the plurality of digitizers comprises:
an operational amplifier; and
an analog to digital converter (ADC), coupled to the operational amplifier.

5. The IC testing interface of claim 1 , wherein the processing means is a field-programmable gate array (FPGA), an application specific integrated circuit (ASIC), a microprocessor, or a micro-controller.

6. The IC testing interface of claim 1 , wherein the IC testing interface is a replaceable interface.

7. The IC testing interface of claim 1 , wherein the semiconductor device is a liquid crystal display driver IC.

8. The IC testing interface of claim 1 , wherein the connection unit comprises a Universal Serial Bus (USB).

9. An automatic test equipment (ATE) for testing a semiconductor device, comprising:
a tester;
a prober, configured for carrying the semiconductor device;
a probe card, coupled to the tester for probing the semiconductor device; and
an integrated circuit (IC) testing interface, coupled to the tester and installed outside of the tester, the IC testing interface comprising:
at least one pin, configured for receiving or transmitting at least one test signal to the tester;
a plurality of digitizers, coupled to the at least one pin for generating a digital signal;
a processing means, coupled to the plurality of digitizers for processing the digital signal; and
a connection unit, configured for connecting the processing means with a computing device for transmitting an output signal from the processing means to the computing device;

wherein the IC testing interface is disposed between the tester and the prober of the ATE;
wherein the at least one pin comprises:
a first pin, configured for transmitting a first test signal of the at least one test signal to the tester of the ATE, wherein the first test signal comprises an enabling signal for reading or writing a testing datum;
a second pin, configured for transmitting a second test signal of the at least one test signal to the tester of the ATE, wherein the second test signal comprises a sampling signal for determining a sampling number of the semiconductor device; and
a third pin, configured for transmitting a third test signal of the at least one test signal to the tester of the ATE, wherein the third test signal comprises a testing result.

10. The ATE of claim 9 , wherein the processing means converts or sorts the digital signal, calibrates an offset of the digital signal, or takes an arithmetic operation on the digital signal.

11. The ATE of claim 9 , wherein the IC testing interface integrates a probe interface board, a load board, or a probe board so as to be installed in the ATE.

12. The ATE of claim 9 , wherein each of the plurality of digitizers comprises:
an operational amplifier; and
an analog to digital converter (ADC), coupled to the operational amplifier.

13. The ATE of claim 9 , wherein the processing means is a field-programmable gate array (FPGA), an application specific integrated circuit (ASIC), a microprocessor, or a micro-controller.

14. The ATE of claim 9 , wherein the IC testing interface is a replaceable interface.

15. The ATE of claim 9 , wherein the semiconductor device is a liquid crystal display driver IC.

16. The IC testing interface of claim 9 , wherein the connection unit comprises a Universal Serial Bus (USB).

Assignees

• Sitronix Technology Corp

Inventors

• Chen Chun-Chi
• Lai Hung-Wei
• Lee Tsung-Jun

Classifications

• G01R31/31905

  Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture · CPC title

• G01R31/31908 Primary

  Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• G01R31/2601 Primary

  Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title