Testing device and a circuit arrangement

Patent metadata

Field	Value
Publication number	US-9488674-B2
Application number	US-201414326483-A
Country	US
Kind code	B2
Filing date	Jul 9, 2014
Priority date	Jul 9, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A testing device in accordance with various embodiments may include: a plurality of first terminals configured to be connected to a plurality of devices-under-test, wherein each first terminal of the plurality of first terminals may be configured to be connected to a respective device-under-test of the plurality of devices-under-test; a signal interface configured to be connected to a tester; and a circuit configured to exchange an identical first signal with each device-under-test of the plurality of devices-under-test through a respective first terminal of the plurality of first terminals, and to exchange at least one interface signal with the tester through the signal interface.

First claim

What is claimed is:

1. A testing device, comprising:
a plurality of first terminals configured to be connected to a plurality of devices-under-test, wherein each first terminal of the plurality of first terminals is configured to be connected to a respective device-under-test of the plurality of devices-under-test;
a signal interface configured to be connected to a tester; and
a circuit configured to exchange an identical first signal with each device-under-test of the plurality of devices-under-test through a respective first terminal of the plurality of first terminals, and to exchange at least one interface signal with the tester through the signal interface; and
wherein the identical first signal comprises a test response signal, and wherein the test response signal is a response of a device-under-test of the plurality of devices-under-test to an identical test signal provided to each device-under-test of the plurality of devices-under-test.

2. The testing device of claim 1 ,
wherein the respective first terminal is configured to be connected to a respective pin of the respective device-under-test, and wherein the respective pins of the respective devices-under-test are configured to provide the same function in each respective device-under-test.

3. The testing device of claim 1 ,
wherein the circuit is configured to provide the identical first signal to each device-under-test of the plurality of devices-under-test via the respective first terminal.

4. The testing device of claim 1 ,
wherein the identical first signal comprises an identical test signal for testing each device-under-test of the plurality of devices-under-test.

5. The testing device of claim 1 ,
wherein the at least one interface signal comprises a reference signal, and
wherein the circuit is configured to receive the reference signal from the tester via the signal interface, and to replicate the reference signal to form the identical first signal exchanged with each device-under-test of the plurality of devices-under-test.

6. The testing device of claim 1 ,
wherein the circuit comprises at least one signal replicator configured to replicate a reference signal to form the identical first signal exchanged with each device-under-test of the plurality of devices-under-test.

7. The testing device of claim 1 ,
wherein the circuit is configured to receive the identical first signal from each device-under-test of the plurality of devices-under-test via the respective first terminal.

8. The testing device of claim 1 ,
wherein the at least one interface signal comprises at least one signal reference, and
wherein the circuit is configured to receive the at least one signal reference from the tester via the signal interface.

9. The testing device of claim 1 ,
wherein the circuit is further configured to store at least one trigger time,
wherein the at least one trigger time is a time at which at least one of a voltage and/or a current of the identical first signal is at least substantially equal to at least one signal reference provided to the circuit.

10. The testing device of claim 9 ,
wherein the at least one interface signal comprises information about the at least one trigger time, and
wherein the circuit is configured to provide the information about the at least one trigger time to the tester through the signal interface.

11. The testing device of claim 1 ,
wherein the at least one interface signal comprises a synchronization signal configured to synchronize the testing device with the tester, and
wherein the circuit is configured to receive the synchronization signal from the tester via the signal interface.

12. The testing device of claim 1 , further comprising:
a plurality of power supply terminals configured to provide a power supply potential to each device-under-test of the plurality of devices-under-test.

13. The testing device of claim 1 ,
wherein the circuit comprises at least one measurement device configured to measure at least one of a voltage and/or a current of the identical first signal.

14. The testing device of claim 1 ,
wherein the circuit comprises at least one comparator configured to compare at least one of a voltage and/or a current of the identical first signal with at least one signal reference provided to the circuit.

15. The testing device of claim 1 , further comprising:
at least one voltage supply configured to provide a power supply potential to the circuit.

16. The testing device of claim 1 ,
wherein the circuit comprises a serial peripheral interface bus.

17. The testing device of claim 1 ,
wherein the circuit comprises a peripheral controller.

18. The testing device of claim 1 , further comprising:
a plurality of second terminals configured to be connected to the plurality of devices-under-test, wherein each second terminal of the plurality of second terminals is configured to be connected to a respective device-under-test,
wherein the circuit is configured to provide the identical first signal to each device-under-test of the plurality of devices-under-test via the respective first terminal of the plurality of first terminals, and to receive an identical second signal from each device-under-test of the plurality of devices-under-test through a respective second terminal of the plurality of second terminals.

19. A circuit arrangement, comprising:
a plurality of devices-under-test;
a tester;
at least one first testing device configured to provide an identical first signal to the plurality of devices-under-test, and to exchange at least one first interface signal with the tester; wherein the identical first signal comprises a test response signal, and wherein the test response signal is a response of a device-under-test of the plurality of devices-under-test to an identical test signal provided to each device-under-test of the plurality of devices-under-test; and
at least one second testing device configured to receive an identical second signal from the plurality of devices-under-test, and to exchange at least one second interface signal with the tester,
wherein a testing device of at least one first testing device and the at least one second testing device comprises a plurality of first terminals configured to be connected to the plurality of devices-under-test, wherein each first terminal of the plurality of first terminals is configured to be connected to a respective device-under-test of the plurality of devices-under-test.

20. A circuit arrangement, comprising:
a plurality of devices-under-test;
a control circuit;
at least one first testing device configured to provide an identical first signal to the plurality of devices-under-test, and to exchange at least one first interface signal with the control circuit; wherein the identical first signal comprises a test response signal, and wherein the test response signal is a response of a device-under-test of the plurality of devices-under-test to an identical test signal provided to each device-under-test of the plurality of devices-under-test; and
at least one second testing device configured to receive an identical second signal from the plurality of devices-under-test, and to exchange at least one second interface signal with the control circuit,
wherein a testing device of at least one first testing device and the at least one second testing device comprises a plurality of first terminals configured to be connected to the plurality of devices-under-test, wherein each first terminal of the plurality of first

Assignees

• Infineon Technologies Ag

Inventors

• Marques Martins Carlos
• Thiele Steffen
• Theil Aron

Classifications

• G01R1/0416 Primary

  Connectors, terminals (G01R1/0425 and G01R1/0433 take precedence; with measurement function for battery poles G01R31/364) · CPC title

• G01R31/31905 Primary

  Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture · CPC title