Semiconductor device

Patent metadata

Field	Value
Publication number	US-2025261388-A1
Application number	US-202519193491-A
Country	US
Kind code	A1
Filing date	Apr 29, 2025
Priority date	May 30, 2023
Publication date	Aug 14, 2025
Grant date	—

Abstract

A semiconductor device, including: a semiconductor substrate having an active region and a termination region; a first semiconductor region provided in the semiconductor substrate; a second semiconductor region provided in the active region, between a front surface of the semiconductor substrate and the first semiconductor region; a vertical device structure provided in the active region; an insulating layer that covers the front surface of the semiconductor substrate in the termination region; a voltage withstanding structure provided in the termination region to surround the active region, and including a third semiconductor region; a channel stopper electrode provided on the insulating layer, closer to the semiconductor substrate than is the voltage withstanding structure; and a fourth semiconductor region provided between the front surface of the semiconductor substrate and the first semiconductor region, apart from the third semiconductor region and the contact hole on two sides of the fourth semiconductor region.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a semiconductor substrate having an active region and a termination region surrounding a periphery of the active region in a plan view of the semiconductor device, the semiconductor substrate having a front surface and a back surface opposite each other; a first semiconductor region of a first conductivity type, provided in the semiconductor substrate, spanning the active region and the termination region; a second semiconductor region of a second conductivity type, provided in the active region of the semiconductor substrate, between the front surface of the semiconductor substrate and the first semiconductor region, thereby forming a pn junction between the second semiconductor region and the first semiconductor region; a vertical device structure provided in the active region and through which a current flows between the front surface and the back surface of the semiconductor substrate, the current passing through the pn junction; an insulating layer that covers the front surface of the semiconductor substrate in the termination region, the insulating layer having a contact hole formed therein; a voltage withstanding structure provided in the termination region to surround the periphery of the active region in the plan view, the voltage withstanding structure being between the front surface of the semiconductor substrate and the first semiconductor region, and including a third semiconductor region of the second conductivity type; a channel stopper electrode provided on the insulating layer, closer to an end of the semiconductor substrate than is the voltage withstanding structure, the channel stopper electrode being in contact with the front surface of the semiconductor substrate via the contact hole in the insulating layer; and a fourth semiconductor region of the first conductivity type, provided between the front surface of the semiconductor substrate and the first semiconductor region, apart from the third semiconductor region and the contact hole that are on two sides of the fourth semiconductor region, the fourth semiconductor region being directly below an inner end of the channel stopper electrode via the insulating layer and having a dopant concentration that is higher than a dopant concentration of the first semiconductor region.

2 . The semiconductor device according to claim 1 , wherein the dopant concentration of the fourth semiconductor region is of a Gaussian distribution in which the dopant concentration decreases from a peak concentration thereof to the front surface of the semiconductor substrate in a depth direction of the semiconductor substrate, and decreases from the peak concentration to the back surface of the semiconductor substrate in the depth direction.

3 . The semiconductor device according to claim 2 , wherein in the depth direction, a distance from the peak concentration to the front surface of the semiconductor substrate is not more than a halfwidth of the Gaussian distribution.

4 . The semiconductor device according to claim 2 , wherein in the depth direction, a depth of the fourth semiconductor region is smaller than a depth of the third semiconductor region.

5 . The semiconductor device according to claim 4 , wherein the depth of the fourth semiconductor region is in a range of 10% to 60% of the depth of the third semiconductor region.

6 . The semiconductor device according to claim 1 , wherein the fourth semiconductor region has a first portion and a second portion that are mutually exclusive, the first portion being closer to the active region than is the inner end of the channel stopper electrode, and the second portion facing the channel stopper electrode via the insulating layer.

7 . The semiconductor device according to claim 6 , wherein in a direction parallel to the front surface of the semiconductor substrate, a width of the first portion of the fourth semiconductor region is not more than a half of a distance from the channel stopper electrode to the third semiconductor region.

8 . The semiconductor device according to claim 6 , wherein
the third semiconductor region is provided in a plurality; the voltage withstanding structure further has a plurality of metal electrodes provided at the front surface of the semiconductor substrate, equal in number to the plurality of the third semiconductor regions, and being respectively in contact with the plurality of third semiconductor regions, each of the plurality of third semiconductor regions and the plurality of metal electrodes having a floating potential, and in a direction parallel to the front surface of the semiconductor substrate, a width of the first portion of the fourth semiconductor region is not more than a half of a distance from the channel stopper electrode to an outermost one of the plurality of third semiconductor regions or an outermost one of the plurality of metal electrodes, whichever is closer to the end of the semiconductor substrate.

9 . The semiconductor device according to claim 6 , wherein in a direction parallel to the front surface of the semiconductor substrate, a width of the second portion of the fourth semiconductor region is in a range of 40% to 60% of a width of the fourth semiconductor region.

10 . The semiconductor device according to claim 4 , further comprising a fifth semiconductor region provided between the front surface of the semiconductor substrate and the first semiconductor region, closer to the end of the semiconductor substrate than is the fourth semiconductor region, the fifth semiconductor region being in contact with the channel stopper electrode via the contact hole, wherein
in the depth direction, the depth of the fourth semiconductor region is smaller than a depth of the fifth semiconductor region.

11 . The semiconductor device according to claim 1 , further comprising a fifth semiconductor region provided between the front surface of the semiconductor substrate and the first semiconductor region, closer to the end of the semiconductor substrate than is the fourth semiconductor region, the fifth semiconductor region being in contact with the channel stopper electrode via the contact hole, wherein
in a direction parallel to the front surface of the semiconductor substrate, the fourth semiconductor region is provided closer to the fifth semiconductor region than is the third semiconductor region.

12 . The semiconductor device according to claim 11 , wherein, the fifth semiconductor region is of the second conductivity type.

13 . The semiconductor device according to claim 2 , further comprising a sixth semiconductor region of the first conductivity type, provided between the second semiconductor region and the first semiconductor region, the sixth semiconductor region having a dopant concentration higher than the dopant concentration of the first semiconductor region, wherein
the dopant concentration of the sixth semiconductor region has a distribution that is the same as that of the dopant concentration of the fourth semiconductor region.

Assignees

• Fuji Electric Co Ltd

Inventors

• KARAMOTO Yuki
• SHIRAKAWA Tohru
• Mitsuzuka Kaname

Classifications

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10D12/415 Primary

  having edge termination structures · CPC title

• H10D12/418

  having a drift region having a doping concentration that is higher at the emitter side relative to other parts of the drift region · CPC title

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title

• H10D64/112

  comprising multiple field plate segments · CPC title