Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-10096703-B2
Application number	US-201615279490-A
Country	US
Kind code	B2
Filing date	Sep 29, 2016
Priority date	Nov 13, 2015
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A recess where an edge termination region is lower than an active region is disposed on a silicon carbide base body and an n − -type silicon carbide layer is exposed at a bottom of the recess. In the portion of the n − -type silicon carbide layer exposed at the bottom of the recess, first and second JTE regions configuring a JTE structure are disposed. The first JTE region is disposed from the bottom of the recess, along a side wall and covers a bottom corner portion of the recess. The first JTE region overlaps an outermost first p-type base region at the bottom corner portion. The first JTE region has an impurity concentration that is highest at the portion overlapping the first p-type base region and distribution of the impurity concentration in a depth direction peaks at a portion deeper than the bottom of the recess.

First claim

What is claimed is:

1. A semiconductor device comprising:
an active region in which main current flows, the active region disposed on a semiconductor substrate of a first conductivity type and formed of a semiconductor material having a band gap that is wider than that of silicon;
an edge termination region surrounding a periphery of the active region;
a recess where the edge termination region is lower than the active region, disposed on a front surface of the semiconductor substrate;
a first semiconductor region of a second conductivity type, selectively disposed on a front surface side of the semiconductor substrate in the active region and extending to under a first face formed in the edge termination region by the recess; and
semiconductor regions of the second conductivity type disposed in the first face to have a concentric ring-shape surrounding the periphery of the active region and to have progressively lower impurity concentrations as proximity to an outer side increases, wherein
an innermost semiconductor region among the semiconductor regions of the second conductivity type is disposed from the first face, along a third face between the first face and a second face farther on the active region side than the recess,
an upper portion of the innermost semiconductor region is positioned to overlap, in a depth direction, a portion of the first semiconductor region, at a boundary of the first face and the third face, and
a lower portion of the innermost semiconductor region extends farther in the depth direction than the upper portion.

2. The semiconductor device according to claim 1 , wherein
the innermost semiconductor region has an impurity concentration that is highest at the lower portion.

3. The semiconductor device according to claim 1 , wherein
a thickness of the innermost semiconductor region is thicker than a thickness of the first semiconductor region, at the first face.

4. The semiconductor device according to claim 1 , wherein
the third face is sloped to form an obtuse angle with the first face.

5. The semiconductor device according to claim 1 , further comprising:
a second semiconductor region of the first conductivity type, selectively disposed in the first semiconductor region;
a gate insulating film disposed to contact a region of the first semiconductor region between the second semiconductor region and the semiconductor substrate;
a gate electrode disposed via the gate insulating film, on a side opposite the first semiconductor region;
a first electrode disposed to contact the first semiconductor region and the second semiconductor region; and
a second electrode disposed to contact a back surface of the semiconductor substrate.

6. The semiconductor device according to claim 1 , wherein
the semiconductor material having a band gap that is wider than that of silicon is silicon carbide.

7. A method of manufacturing a semiconductor device including an active region disposed on a semiconductor substrate of a first conductivity type and formed from a semiconductor material having a band gap that is wider than that of silicon, and an edge termination region surrounding a periphery of the active region, the method comprising:
forming on a front surface of the semiconductor substrate, a recess where the edge termination region is lower than the active region;
selectively forming on a front surface side of the semiconductor substrate in the active region, a first semiconductor region of a second conductivity type, the first semiconductor region formed to extend under a first face formed in the edge termination region by the recess; and
forming in the first face, semiconductor regions of the second conductivity type, the semiconductor regions formed to have a concentric ring-shape surrounding the periphery of the active region and to have progressively lower impurity concentrations as proximity to an outer side increases, wherein
forming the semiconductor regions of the second conductivity type includes forming an innermost semiconductor region among the semiconductor regions of the second conductivity type from the first face, along a third face between the first face and a second face farther on the active region side than the recess,
forming an upper portion of the innermost semiconductor region to overlap, in a depth direction, a portion of the first semiconductor region, at a boundary of the first face and the third face, and
forming a lower portion of the innermost semiconductor region to extend farther in the depth direction than the upper portion.

8. The semiconductor device according to claim 1 , wherein the upper portion and the lower portion of the innermost semiconductor region occupy a same area in part, in the depth direction, as the portion of the first semiconductor region.

9. The semiconductor device according to claim 2 , wherein the first semiconductor region of the second conductivity type includes a first base region and a second base region located over the first base region, the portion of the innermost semiconductor region having the impurity concentration that is highest being located in the first base region, and a portion of the innermost semiconductor region occupying a same area in part as the second base region having a lower impurity concentration than the portion of the innermost semiconductor region located in the first base region.

Assignees

• Fuji Electric Co Ltd

Inventors

• Harada Yuichi
• Hoshi Yasuyuki

Classifications

• H10D12/032

  of vertical IGBTs · CPC title

• H10D12/418

  having a drift region having a doping concentration that is higher at the emitter side relative to other parts of the drift region · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D12/415

  having edge termination structures · CPC title

• H01L29/1608

  Electricity · mapped topic