Semiconductor device and manufacturing method thereof

US10181508B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10181508-B2
Application numberUS-201715445991-A
CountryUS
Kind codeB2
Filing dateMar 1, 2017
Priority dateMar 16, 2016
Publication dateJan 15, 2019
Grant dateJan 15, 2019

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a guard ring section to which a fine processing is easily applied. Provided is a semiconductor device comprising: a semiconductor substrate; an active region formed in the semiconductor substrate; and a guard ring section formed more outside than the active region in the semiconductor substrate, wherein the guard ring section includes: a guard ring formed in a circular pattern on an upper surface of the semiconductor substrate; an interlayer insulating film formed above the guard ring; a field plate formed in a circular pattern along the guard ring and above the interlayer insulating film; and a tungsten plug formed in a circular pattern along the guard ring and penetrating the interlayer insulating film to connect the guard ring and the field plate.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a semiconductor substrate; an active region formed in the semiconductor substrate; and a guard ring section formed more outside than the active region in the semiconductor substrate, wherein the guard ring section includes: a guard ring formed in a circular pattern on an upper surface of the semiconductor substrate, the guard ring being a single doped region; an interlayer insulating film formed above the guard ring; a field plate formed in a circular pattern along the guard ring and above the interlayer insulating film; two tungsten plugs formed in a circular pattern along the guard ring and penetrating the interlayer insulating film to connect the guard ring and the field plate, the two tungsten plugs being in direct physical contact with the guard ring and the field plate; and a connection plug connecting the two tungsten plugs at one or more portions of each tungsten plug. 2. The semiconductor device according to claim 1 , wherein the field plate is formed of tungsten. 3. The semiconductor device according to claim 1 , wherein a distance between two adjacent tungsten plugs in the plurality of circular tungsten plugs is larger than a width of one tungsten plug. 4. The semiconductor device according to claim 2 further comprising: an element electrode provided above the active region and formed of aluminum-containing material; a plating layer formed on the element electrode; and a protection film formed on the plating layer and exposing some regions of the plating layer. 5. The semiconductor device according to claim 1 further comprising: a semiconductor element section formed in the active region; and a hole diverting plug provided between the semiconductor element section and the guard ring section to penetrate the interlayer insulating film and formed of tungsten. 6. The semiconductor device according to claim 1 further comprising an element electrode provided above the active region, wherein the field plate is formed of same material as that of the element electrode. 7. The semiconductor device according to claim 1 , wherein each tungsten plug has one end in direct physical contact with the field plate and the other end in direct physical contact with the guard ring. 8. A manufacturing method of a semiconductor device comprising: forming a guard ring in a circular pattern on an upper surface of a semiconductor substrate, the guard ring being a single doped region; forming an interlayer insulating film above the guard ring; and simultaneously forming a plurality of tungsten plugs provided in a circular pattern on the guard ring to penetrate the interlayer insulating film and a field plate in a circular pattern provided along the guard ring and above the interlayer insulating film to connect to the plurality of tungsten plugs, the plurality of tungsten plugs being in direct physical contact with the guard ring and the field plate. 9. The manufacturing method according to claim 8 further comprising: forming an element electrode of aluminum-containing material in an active region surrounded by the guard ring on the upper surface of the semiconductor substrate; forming a plating layer on the element electrode after the forming the element electrode and the forming the field plate by plating the upper surface side of the semiconductor substrate; and forming a protection film at the upper surface side of the semiconductor substrate after the plating. 10. The manufacturing method according to claim 8 , wherein each tungsten plug has one end in direct physical contact with the field plate and the other end in direct physical contact with the guard ring.

Assignees

Inventors

Classifications

  • using a liquid · CPC title

  • the connected ends being wedge-shaped · CPC title

  • the connected ends being ball-shaped · CPC title

  • Bond pads, in general · CPC title

  • Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

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Frequently asked questions

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What does patent US10181508B2 cover?
Provided is a guard ring section to which a fine processing is easily applied. Provided is a semiconductor device comprising: a semiconductor substrate; an active region formed in the semiconductor substrate; and a guard ring section formed more outside than the active region in the semiconductor substrate, wherein the guard ring section includes: a guard ring formed in a circular pattern on an…
Who is the assignee on this patent?
Fuji Electric Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L29/0619. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 15 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).