Semiconductor device

Patent metadata

Field	Value
Publication number	US-2025054906-A1
Application number	US-202318447321-A
Country	US
Kind code	A1
Filing date	Aug 10, 2023
Priority date	Aug 10, 2023
Publication date	Feb 13, 2025
Grant date	—

Abstract

A semiconductor device includes an interposer, a first die, a second die, a third die and a dummy die. The interposer includes a first region and a second region. The first die and the second die are bonded to a first surface of the interposer, the first die is disposed in the first region, and the second die is disposed in the second region. The third die and the dummy die are bonded to a second surface opposite to the first surface of the interposer, wherein the third die is disposed in the first region and the dummy die is disposed in the second region.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
an interposer, comprising a first region and a second region; a first die and a second die, bonded to a first surface of the interposer, the first die disposed in the first region, and the second die disposed in the second region; and a third die and a dummy die, bonded to a second surface opposite to the first surface of the interposer, wherein the third die is disposed in the first region and the dummy die is disposed in the second region.

2 . The semiconductor device of claim 1 , wherein the first die and the third die are overlapped along a stacking direction of the first die and the interposer, and the second die and the dummy die are overlapped along the stacking direction.

3 . The semiconductor device of claim 1 , wherein the third die is electrically connected to the first die through the interposer, and the dummy die is electrically isolated from the second die.

4 . The semiconductor device of claim 1 , wherein the interposer comprises at least one active conductive pattern and at least one dummy conductive pattern, the third die is electrically connected to the at least one active conductive pattern, and the dummy die is electrically connected to the at least one dummy conductive pattern.

5 . The semiconductor device of claim 4 , wherein the at least one active conductive pattern and the at least one dummy conductive pattern are provided within a same dielectric layer.

6 . The semiconductor device of claim 1 , further comprising a plurality of conductive connectors disposed on the second surface of the interposer, wherein the third die and the dummy die are respectively disposed between adjacent two of the conductive connectors.

7 . The semiconductor device of claim 1 , further comprising an underfill surrounding the interposer, the third die and the dummy die.

8 . The semiconductor device of claim 1 , wherein the third die is an integrated passive die (IPD), a surface mount device (SMD) or a large scale integrated (LSI) circuit.

9 . A semiconductor device, comprising:
an interposer; a first integrated circuit and a second integrated circuit, bonded to a first surface of the interposer; and a functional die and a dummy die, bonded to a second surface opposite to the first surface of the interposer, wherein the functional die is overlapped with and electrically connected to the first integrated circuit through the interposer, and the dummy die is overlapped with the second integrated circuit.

10 . The semiconductor device of claim 9 , further comprising a first encapsulant disposed on the first surface of the interposer, wherein the first encapsulant encapsulates the first integrated circuit and the second integrated circuit, and a top surface of the first encapsulant is substantially coplanar with top surfaces of the first integrated circuit and the second integrated circuit.

11 . The semiconductor device of claim 9 , further comprising a first encapsulant disposed on the first surface of the interposer and a second encapsulant between the first integrated circuit and the second integrated circuit, wherein the first encapsulant encapsulates the first integrated circuit, the second integrated circuit and the second encapsulant.

12 . The semiconductor device of claim 9 , further comprising a first encapsulant disposed on the first surface of the interposer and a third encapsulant, wherein the third encapsulant encapsulates the functional die, the dummy die and the first encapsulant.

13 . The semiconductor device of claim 9 , wherein the dummy die comprises a plurality of conductive connectors bonded to the second surface of the interposer without extending into the interposer.

14 . The semiconductor device of claim 9 , further comprising a package substrate, wherein the interposer is bonded to the substrate, and the functional die and the dummy die are disposed between the interposer and the package substrate.

15 . A semiconductor device, comprising:
an interposer, comprising a first region; a first integrated circuit, bonded to a first surface of the interposer and disposed in the first region; and a plurality of functional dies and at least one dummy die, attached to a second surface opposite to the first surface of the interposer, wherein the functional dies and the at least one first dummy die are disposed in the first region.

16 . The semiconductor device of claim 15 , wherein the at least one first dummy die is disposed between the functional dies.

17 . The semiconductor device of claim 15 , wherein the functional dies and the at least one dummy die are disposed in an array.

18 . The semiconductor device of claim 15 , wherein the at least one second dummy die is disposed at a corner region of the first region.

19 . The semiconductor device of claim 15 , further comprising:
a second integrated circuit, bonded to the first surface of the interposer and disposed in a second region of the interposer; and at least one second dummy die, bonded to the second surface opposite to the first surface of the interposer and disposed in the second region of the interposer.

20 . The semiconductor device of claim 15 , further comprising:
a second integrated circuit, bonded to the first surface of the interposer and disposed in a second region of the interposer; and at least one second dummy die, bonded to the second surface opposite to the first surface of the interposer and disposed between the first region and the second region or between the second regions of the interposer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hsien-Wei
• Lin Meng-Liang
• Fan Fu
• Jeng Shin-Puu

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/121 Primary

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title