Semiconductor device, chip and fabrication method thereof, memory system

Patent metadata

Field	Value
Publication number	US-2025054905-A1
Application number	US-202318531542-A
Country	US
Kind code	A1
Filing date	Dec 6, 2023
Priority date	Aug 7, 2023
Publication date	Feb 13, 2025
Grant date	—

Abstract

According to one aspect of the present disclosure, semiconductor device is provided. The semiconductor device may include a plurality of cutting lanes. The plurality of cutting lanes may include at least one first cutting lane. The plurality of cutting lanes may include a plurality of second cutting lanes disposed in parallel with the first cutting lane. The plurality of cutting lanes may include a third cutting lane disposed intersecting the first cutting lane and the second cutting lanes. The semiconductor device may include a plurality of dies defined by the intersection of the plurality of cutting lanes. The semiconductor device may include a die test structure only located in the first cutting lane. Any one of the at least one first cutting lane may be disposed adjacent to at least one of the plurality of second cutting lanes.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a plurality of cutting lanes, comprising:
at least one first cutting lane;
a plurality of second cutting lanes disposed in parallel with the first cutting lane; and
a third cutting lane disposed intersecting the first cutting lane and the second cutting lanes;
a plurality of dies defined by the intersection of the plurality of cutting lanes; and a die test structure only located in the first cutting lane,
wherein any one of the at least one first cutting lane is disposed adjacent to at least one of the plurality of second cutting lanes.

2 . The semiconductor device of claim 1 , wherein at least three of the plurality of second cutting lanes are arranged between adjacent two of at least one first cutting lane.

3 . The semiconductor device of claim 1 , wherein a number of the plurality of the second cutting lanes spaced between adjacent two of the at least one first cutting lane is equal.

4 . The semiconductor device of claim 1 , wherein:
a cutting lane of the plurality of cutting lanes comprises first dielectric layers second dielectric layers stacked alternatively, the die test structure penetrates the plurality of cutting lanes in a stacking direction, and the die test structure comprises third dielectric layers and conductive layers stacked alternatively in the stacking direction.

5 . The semiconductor device of claim 4 , wherein a thickness of the die test structure is smaller than or equal to a thickness of the cutting lane.

6 . The semiconductor device of claim 5 , wherein:
the die test structure comprises a plurality of die test structures, and die test structures with a same thickness are located in a same first cutting lane.

7 . The semiconductor device of claim 4 , further comprising:
a semiconductor layer; and a stack on the semiconductor layer, the stack comprising the third dielectric layers and the conductive layers stacked alternatively in the stacking direction,
wherein the plurality of cutting lanes and the die test structure are located on the semiconductor layer.

8 . The semiconductor device of claim 1 , wherein:
a die of the plurality of dies comprises:
a memory device and a peripheral circuit bonded with each other, and
the die test structure is configured for an electric performance test of the memory device, the peripheral circuit, or a bonding interface between the memory device and the peripheral circuit.

9 . The semiconductor device of claim 1 , wherein:
the plurality of cutting lanes and the plurality of dies form a repeating unit, the repeating unit comprises the at least one first cutting lane, and the semiconductor device comprises a plurality of the repeating units.

10 . A chip fabricated from a semiconductor device, comprising:
a stack, comprising:
a plurality of alternating conductive layers and dielectric layers; and
a plurality of channel structures;
a first cutting face at an outer edge of the stack; and a second cutting face outside the first cutting face,
wherein the second cutting face has a height smaller than a height of the first cutting face.

11 . A method of fabricating a chip, comprising:
providing a semiconductor device provided with a plurality of cutting lanes, the plurality of cutting lanes comprising at least one first cutting lane, a plurality of second cutting lanes, and a third cutting lane, wherein the at least one first cutting lane and the plurality of second cutting lanes are disposed in parallel with each other, and the third cutting lane is disposed intersecting the at least one first cutting lane and the plurality of second cutting lanes, and a die test structure is disposed in the first cutting lane; and cutting the semiconductor device into a plurality of chips along the first cutting lane, the second cutting lane, and the third cutting lane.

12 . The method of claim 11 , wherein the cutting the semiconductor device into a plurality of chips along the at least one first cutting lane, the plurality of second cutting lanes, and the third cutting lane comprises:
cutting the semiconductor device twice with two different cutting processes, respectively.

13 . The method of claim 12 , wherein the cutting the semiconductor device into a plurality of chips along the at least one first cutting lane, the plurality of second cutting lanes, and the third cutting lane comprises:
forming a first groove in the first cutting lane with a first laser to remove a part of the die test structure, wherein a depth of the first groove is smaller than a thickness of the first cutting lane; and mechanically cutting the plurality of second cutting lanes, the third cutting lane, and the at least one first cutting lane under the first groove to form a plurality of chips.

14 . The method of claim 13 , wherein:
before cutting the first cutting lane under the first groove, the plurality of second cutting lanes and the third cutting lane with a blade, the method further comprises:
forming a second groove in the plurality of second cutting lanes and forming a third groove in the third cutting lane with a second laser, wherein a depth of the second groove is smaller than a thickness of the plurality of second cutting lanes, and a depth of the third groove is smaller than a thickness of the third cutting lane; and
the cutting mechanically the plurality of second cutting lanes, the third cutting lane, and the first cutting lane under the first groove comprises:
cutting the first cutting lane under the first groove, the plurality of second cutting lanes under the second groove and the third cutting lane under the third groove with the blade.

15 . The method of claim 14 , wherein an energy of the second laser is smaller than an energy of the first laser.

16 . The method of claim 11 , wherein the semiconductor device further comprises:
a plurality of dies defined by an intersection of the plurality of cutting lanes; and a die test structure only located in the first cutting lane,
wherein any one of the at least one first cutting lane is disposed adjacent to at least one of the plurality of second cutting lanes.

17 . The method of claim 16 , wherein:
a cutting lane of the plurality of cutting lanes comprises first dielectric layers second dielectric layers stacked alternatively, the die test structure penetrates the plurality of cutting lanes in a stacking direction, and the die test structure comprises third dielectric layers and conductive layers stacked alternatively in the stacking direction.

18 . The method of claim 17 , wherein a thickness of the die test structure is smaller than or equal to a thickness of the cutting lane.

19 . The method of claim 11 , wherein at least three of the plurality of second cutting lanes are arranged between adjacent two of at least one first cutting lane.

20 . The method of claim 11 , wherein a number of the plurality of the plurality of second cutting lanes spaced between adjacent two of the at least one first cutting lane is equal.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Mo Ping
• Chen Peng
• Xie Wei
• Fang Hong
• Liu Lei
• Xia Zhiliang

Classifications

• H10W72/0198

  batch processes · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10B80/00 Primary

  Assemblies of multiple devices comprising at least one memory device covered by this subclass · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title