Semiconductor device

Patent metadata

Field	Value
Publication number	US-2020058543-A1
Application number	US-201916420328-A
Country	US
Kind code	A1
Filing date	May 23, 2019
Priority date	Aug 17, 2018
Publication date	Feb 20, 2020
Grant date	—

Abstract

A semiconductor device including a semiconductor substrate including a chip region and an edge region around the chip region; a lower dielectric layer and an upper dielectric layer on the semiconductor substrate; a redistribution chip pad that penetrates the upper dielectric layer on the chip region and is connected a chip pad; a process monitoring structure on the edge region; and dummy elements in the edge region and having an upper surface lower than an upper surface of the upper dielectric layer.

First claim

1 . A semiconductor device, comprising:
a semiconductor substrate including a chip region and an edge region around the chip region; a lower dielectric layer and an upper dielectric layer on the semiconductor substrate; a redistribution chip pad that penetrates the upper dielectric layer on the chip region and is connected a chip pad; a process monitoring structure on the edge region; and dummy elements in the edge region and having an upper surface lower than an upper surface of the upper dielectric layer.

2 . The semiconductor device as claimed in claim 1 , wherein the dummy element are part of the process monitoring structure and include:
a plurality of dummy metal structures spaced apart from each other in the lower dielectric layers; and a dummy metal pattern covering the dummy metal structures, wherein the upper dielectric layer covers the dummy metal pattern.

3 . The semiconductor device as claimed in claim 1 , wherein the dummy elements include a plurality of dummy redistribution patterns that penetrate the upper dielectric layer in the edge region.

4 . The semiconductor device as claimed in claim 3 , wherein, when viewed in plan, the dummy redistribution patterns are around the process monitoring pattern.

5 . The semiconductor device as claimed in claim 1 , wherein the process monitoring structure further includes a plurality of redistribution alignment patterns in the upper dielectric layer, the redistribution alignment patterns contacting the dummy metal pattern.

6 . The semiconductor device as claimed in claim 1 , wherein the plurality of dummy metal structures each include:
a plurality of stacked dummy metal lines that extend in one direction; and a plurality of dummy metal vias that are connected between the dummy metal lines.

7 . The semiconductor device as claimed in claim 1 , wherein, when viewed in plan, the dummy metal pattern overlaps the plurality of dummy metal structures.

8 . The semiconductor device as claimed in claim 1 , wherein the dummy metal pattern has a plurality of alignment holes that are spaced apart from each other, the alignment holes being filled with the upper dielectric layer.

9 . The semiconductor device as claimed in claim 1 , wherein the upper dielectric layer has a second opening spaced apart from the process monitoring structure and exposing a portion of the lower dielectric layer on the edge region.

10 . The semiconductor device as claimed in claim 9 , wherein
the lower dielectric layer has a first thickness on the chip region, and the portion of the lower dielectric layer has a second thickness that is less than the first thickness, the portion of the lower dielectric layer being exposed to the second opening.

11 . (canceled)

12 . The semiconductor device as claimed in claim 1 , wherein:
the dummy metal structures include a first metallic material, and the dummy metal pattern includes a second metallic material that is different from the first metallic material.

13 . The semiconductor device as claimed in claim 1 , wherein:
the upper dielectric layer includes:
a first upper dielectric layer that covers the chip pad; and
a second upper dielectric layer and a third upper dielectric layer that are stacked on the first upper dielectric layer, and
the second upper dielectric layer includes a dielectric material that is different from dielectric materials of the first upper dielectric layer and the third upper dielectric layer.

14 . The semiconductor device as claimed in claim 1 , further comprising:
a semiconductor integrated circuit on the semiconductor substrate of the chip region; and a plurality of metal lines and a plurality of metal vias in the lower dielectric layers of the chip region, the metal lines and the metal vias connecting the semiconductor integrated circuit to the chip pad.

15 . The semiconductor device as claimed in claim 1 , further comprising a passivation layer on the upper dielectric layer of the chip region and exposing a portion of the redistribution chip pad.

16 . The semiconductor device as claimed in claim 15 , wherein the passivation layer extends toward the edge region and covers the process monitoring structure.

17 . A semiconductor device, comprising:
a semiconductor substrate including a chip region and an edge region around the chip region; a lower dielectric layer and an upper dielectric layer on the semiconductor substrate; a redistribution chip pad that penetrates the upper dielectric layer on the chip region and is connected to a chip pad; a process monitoring pattern on the edge region; and a plurality of dummy redistribution patterns that penetrate the upper dielectric layer on the edge region, wherein, when viewed in plan, the dummy redistribution patterns are around the process monitoring pattern.

18 . The semiconductor device as claimed in claim 17 , wherein the plurality of dummy redistribution patterns includes:
a plurality of first dummy redistribution patterns each having a first thickness, the plurality of first dummy redistribution patterns surrounding the process monitoring pattern when viewed in plan; and a plurality of second dummy redistribution patterns between the plurality of first dummy redistribution patterns and the process monitoring pattern, the plurality of second dummy redistribution patterns each having a second width that is less than the first width.

19 . The semiconductor device as claimed in claim 18 , wherein bottom surfaces of the plurality of first dummy redistribution patterns are located at a level that is lower than that of bottom surfaces of the plurality of second dummy redistribution patterns.

20 . The semiconductor device as claimed in claim 17 , wherein each of the plurality of dummy redistribution patterns includes:
a bottom segment in contact with the lower dielectric layer; and a plurality of sidewall segments that extend from the bottom segment.

21 . The semiconductor device as claimed in claim 20 , further comprising a passivation layer on the upper dielectric layer of the chip region and exposing a portion of the redistribution chip pad,
wherein the passivation layer extends toward the edge region, the passivation layer filling a gap defined by the bottom segment and the sidewall segments of each of the dummy redistribution patterns.

22 .- 26 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Jung-Hoon
• Kim Seokhwan
• Kim Joodong
• Noh Junyong
• Seo Jaewon

Classifications

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title