Scribe lane structure in which pad including via hole is arranged on sawing line

Patent metadata

Field	Value
Publication number	US-10163741-B2
Application number	US-201715677053-A
Country	US
Kind code	B2
Filing date	Aug 15, 2017
Priority date	Dec 28, 2016
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A semiconductor device structure, including integrated circuits of semiconductor chips and scribe lanes between the regions in which the circuits have been formed, has at least one redistribution pad disposed in one of the scribe lanes for simultaneously testing a group of the integrated circuits, and a metal interconnection structure disposed beneath the redistribution pad(s). The metal interconnection structure includes at least conductive via contacting the redistribution pad at the bottom of the pad. The conductive via(s) is/are arranged so that at least a portion of each via remains attached to the redistribution pad when the structure is sawed along the scribe lane.

First claim

What is claimed is:

1. A method of singulating semiconductor chips, the method comprising:
providing a structure including a semiconductor substrate, respective integrated circuits of semiconductor chips arrayed across the semiconductor substrate as spaced from each other by scribe lanes, a redistribution pad in one of the scribe lanes, and at least one conductive via contacting a bottom portion of the redistribution pad, each said at least one conductive via having a widthwise dimension in a direction perpendicular to said one of the scribe lanes; and
cutting a line in the semiconductor substrate along a longitudinal axis of said one of the scribe lanes,
wherein the line along which the semiconductor substrate is cut has a width less than the width of said one of the scribe lanes and less than the widthwise dimension of each said at least one conductive via, and
the line along with the semiconductor substrate is cut is located relative to said at least one conductive via such that one part of each said at least one conductive via is removed by the cutting whereas another part of each said at least one conductive via remains attached to the redistribution pad.

2. The method of claim 1 , wherein the structure provided includes a metal layer on the semiconductor substrate and an intermetallic insulating layer in contact with the metal layer, and each said at least one conductive via extends in the intermetallic insulating layer and contacts the metal layer.

3. The method of claim 2 , wherein the intermetallic insulating layer comprises at least one material selected from the group consisting of an oxide, a nitride, an oxynitride, a low-k dielectric, and an ultra-low-k dielectric.

4. The method of claim 1 , wherein the structure provided includes a plurality of redistribution pads disposed in said one of the scribe lanes, each of the redistribution pads being electrically connected to a group of the integrated circuits of the semiconductor chips such that the integrated circuits of the semiconductor chips of the group can be simultaneously tested via the plurality of redistribution pads.

5. The method of claim 1 , wherein each said at least one conductive via has a central region located along the longitudinal axis of said one of the scribe lanes, and the cutting of the semiconductor substrate cuts through the central region of each said at least one conductive via while leaving opposite side portions of each said at least one conductive via in place.

6. An article of manufacture for use in forming semiconductor chips, comprising:
a semiconductor substrate;
substantially identical integrated circuits arrayed across the semiconductor substrate in chip regions, respectively, the chip regions separated from one another by scribe lanes including a first scribe lane having a central longitudinal axis extending in a first direction and a second scribe lane having a central longitudinal axis extending longitudinally in a second direction crossing the first direction, whereby the first scribe lane and the second scribe lane cross one another in a region between first, second, third and fourth ones of the chip regions;
a first test circuit and a second test circuit disposed in the scribe lanes and spaced from each other on opposite sides of the central longitudinal axis of the first one of the scribe lanes;
a plurality of redistribution pads of electrically conductive material disposed on the semiconductor substrate in the first scribe lane as exposed at an upper part of the first scribe lane, the plurality of redistribution pads being electrically connected to the first and second test circuits;
first redistribution lines electrically connected in the second scribe lane to the first test circuit and electrically connected to the integrated circuits in the first and third ones of the chip regions;
second redistribution lines electrically connected in the second scribe lane to the second test circuit and electrically connected to the integrated circuits in the second and the fourth ones of the chip regions; and
conductive vias contacting the redistribution pads, each of the conductive vias contacting a respective one of the redistribution pads at a bottom portion of the respective one of the redistribution pads,
wherein the plurality of redistribution pads are electrically connected to the integrated circuits in the first, second, third and fourth ones of the chip regions.

7. The article of manufacture of claim 6 , further comprising:
a metal layer disposed on the semiconductor substrate; and
an intermetallic insulating layer interposed between the metal layer and the plurality of redistribution pads, and
wherein each of the redistribution pads is disposed directly on the intermetallic insulating layer, and
each of the conductive vias extends through the intermetallic insulating layer and contacts the metal layer.

8. The article of manufacture of claim 6 , wherein the central longitudinal axis of the first scribe lane passes through a central region of each of the conductive vias.

9. The article of manufacture of claim 6 , wherein two respective ones of the conductive vias contact each said respective one of the redistribution pads at the bottom portion of the respective one of the redistribution pads, the central longitudinal axis of the first scribe lane passes between the two respective ones of the conductive vias, and the two respective ones of the conductive vias are spaced apart from one another along a line crossing the central longitudinal axis.

10. The article of manufacture of claim 6 , wherein the first test circuit and the second test circuit are disposed in the region in which the first scribe lane and the second scribe lane cross each other.

11. The article of manufacture of claim 6 , wherein the plurality of redistribution pads are symmetrical about the central longitudinal axis of the first scribe lane.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Young-Ho
• Song Ho-Sung
• Nam Jeong-Sik
• Kim Kyoung-Min
• Lee Tae-Hyeong

Classifications

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P54/00 Primary

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W46/503

  Located in scribe lines · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title