Semiconductor package

Patent metadata

Field	Value
Publication number	US-2025022866-A1
Application number	US-202418409931-A
Country	US
Kind code	A1
Filing date	Jan 11, 2024
Priority date	Jul 14, 2023
Publication date	Jan 16, 2025
Grant date	—

Abstract

A semiconductor package includes a substrate, a passive element on the substrate, and a connection terminal connecting the substrate to the passive element. The substrate includes a base portion comprising an element pad connected to the connection terminal, and an upper insulating layer on the base portion to expose at least a portion of the base portion. The passive element is in contact with the upper insulating layer, and a thickness of the connection terminal and a thickness of the upper insulating layer are equal to each other.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a substrate; a passive element on the substrate; and a connection terminal connecting the substrate to the passive element, the substrate comprising
a base portion comprising an element pad connected to the connection terminal; and
an upper insulating layer on the base portion to expose at least a portion of the base portion,
the passive element in contact with the upper insulating layer, and a thickness of the connection terminal and a thickness of the upper insulating layer being equal to each other.

2 . The semiconductor package of claim 1 , wherein the thickness of the upper insulating layer is 30 μm or less.

3 . The semiconductor package of claim 1 , wherein
the passive element includes an insulating portion and a conductive portion surrounding the insulating portion, and the conductive portion is electrically connected to the connection terminal.

4 . The semiconductor package of claim 1 , further comprising:
a semiconductor chip on the substrate and spaced apart from the passive element in a first direction; and a connection structure connecting the substrate to the semiconductor chip, wherein the upper insulating layer is spaced apart from the semiconductor chip.

5 . The semiconductor package of claim 1 , wherein
the substrate further comprises vias penetrating the base portion, and the passive element is electrically connected to the vias through the connection terminal and the element pad.

6 . The semiconductor package of claim 1 , wherein
the upper insulating layer comprises an insulating structure and a dam, the passive element is in contact with the dam, and the passive element is spaced apart from the insulating structure.

7 . The semiconductor package of claim 6 , wherein a shape of the dam is a polygonal shape.

8 . The semiconductor package of claim 6 , wherein the dam includes a plurality of dams.

9 . The semiconductor package of claim 6 , wherein
the insulating structure includes:
a first sidewall extending in a first direction;
a second sidewall extending in a second direction intersecting the first direction; and
a corner at which the first sidewall meets the second sidewall, and
the dam is in contact with the corner.

10 . The semiconductor package of claim 6 , wherein
the insulating structure and the dam include a same material, and the insulating structure and the dam are connected to each other without a boundary therebetween.

11 . A semiconductor package comprising:
a substrate; a passive element on the substrate; and a connection terminal connecting the substrate to the passive element,
the substrate comprising a base portion comprising an element pad connected to the connection terminal; and
an upper insulating layer on the base portion to expose at least a portion of the base portion,
the upper insulating layer comprising
a dam in contact with the passive element; and
an insulating structure spaced apart from the passive element, and
the dam being surrounded by the insulating structure.

12 . The semiconductor package of claim 11 , wherein
the insulating structure includes:
a first sidewall extending in a first direction;
a second sidewall extending in a second direction intersecting the first direction;
a third sidewall spaced apart from the first sidewall in the second direction;
a fourth sidewall spaced apart from the second sidewall in the first direction,
a first corner at which the first sidewall meets the second sidewall;
a second corner at which the second sidewall meets the third sidewall;
a third corner at which the third sidewall meets the fourth sidewall; and
a fourth corner at which the first sidewall meets the fourth sidewall.

13 . The semiconductor package of claim 12 , wherein
the dam includes first to fourth dams on the substrate, the first dam is in contact with the first corner, the second dam is in contact with the second corner, the third dam is in contact with the third corner, and the fourth dam is in contact with the fourth corner.

14 . The semiconductor package of claim 12 , wherein
the element pad includes a plurality of element pads, the dam includes first and second dams on the element pads, the first dam is in contact with the second sidewall and is spaced apart from the first corner and the second corner, and the second dam is in contact with the fourth sidewall and is spaced apart from the third corner and the fourth corner.

15 . The semiconductor package of claim 12 , wherein
the element pad includes a plurality of element pads, the dam includes first to fourth dams on the element pads, the first dam is in contact with the first sidewall and is spaced apart from the first corner and the fourth corner, the second dam is in contact with the second sidewall and is spaced apart from the first corner and the second corner, the third dam is in contact with the third sidewall and is spaced apart from the second corner and the third corner, and the fourth dam is in contact with the fourth sidewall and is spaced apart from the third corner and the fourth corner.

16 . The semiconductor package of claim 11 , wherein
a width of the dam in a first direction is 3 mm or less, and a length of the dam in a second direction intersecting the first direction is 3 mm or less.

17 . The semiconductor package of claim 11 , wherein a level of a top surface of the insulating structure is a same level as a level of a bottom surface of the passive element.

18 . The semiconductor package of claim 11 , wherein thicknesses of the connection terminal, the insulating structure and the dam are equal to each other.

19 . A semiconductor package comprising:
a substrate; a passive element on the substrate; a connection terminal connecting the substrate to the passive element; and a molding layer surrounding the passive element and the connection terminal, the substrate comprising
a base portion comprising an element pad connected to the connection terminal; and
an upper insulating layer on the base portion to expose at least a portion of the base portion,
the upper insulating layer comprising
a dam in contact with the passive element; and
an insulating structure spaced apart from the passive element,
the insulating structure including
a first sidewall extending in a first direction;
a second sidewall extending in a second direction intersecting the first direction; and
a corner at which the first sidewall meets the second sidewall,
the dam in contact with the corner, and the connection terminal, the insulating structure and the dam are at a same level.

20 . The semiconductor package of claim 19 , wherein the insulating structure and the dam include different insulating materials.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeong Sanghyeon
• Kim Hyunki
• Lee Junga

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title