Connection structural body and semiconductor device

Patent metadata

Field	Value
Publication number	US-2024021556-A1
Application number	US-202318347904-A
Country	US
Kind code	A1
Filing date	Jul 6, 2023
Priority date	Jul 12, 2022
Publication date	Jan 18, 2024
Grant date	—

Abstract

A connection structural body includes a first connection terminal, a second connection terminal facing the first connection terminal, and a bonding member bonding the first connection terminal and the second connection terminal. The bonding member includes an intermetallic compound layer that is formed by a roughened-surface metal film, structured by deposits of metal piled over one another such that a large number of pores are formed, and a solder layer that is disposed in the pores.

First claim

What is claimed is:

1 . A connection structural body, comprising:
a first connection terminal; a second connection terminal facing the first connection terminal; and a bonding member bonding the first connection terminal and the second connection terminal, wherein the bonding member includes an intermetallic compound layer that is formed by a roughened-surface metal film, structured by deposits of metal piled over one another such that pores are formed, and a solder layer that is disposed in the pores.

2 . The connection structural body according to claim 1 , wherein the intermetallic compound layer includes a portion extending over an entire length of the bonding member in a thickness-wise direction.

3 . The connection structural body according to claim 1 , wherein the intermetallic compound layer is structured by a stack of a first intermetallic compound layer and a second intermetallic compound layer that differs from the first intermetallic compound layer, wherein the second intermetallic compound layer is stacked on the first intermetallic compound layer in a thickness-wise direction of the bonding member.

4 . The connection structural body according to claim 3 , wherein
the roughened-surface metal film is formed from a metal material including copper, the solder layer is formed from a metal material including tin, the first intermetallic compound layer is formed by an intermetallic compound of Cu 6 Sn 5 , and the second intermetallic compound layer is formed by an intermetallic compound of Cu 3 Sn.

5 . The connection structural body according to claim 3 , wherein
the first intermetallic compound layer extends over an entire length of the bonding member in the thickness-wise direction at a central portion of the intermetallic compound layer in plan view, and the second intermetallic compound layer is stacked on the first intermetallic compound layer at an outer edge portion of the intermetallic compound layer in plan view.

6 . The connection structural body according to claim 3 , wherein the first intermetallic compound layer entirely overlaps the second intermetallic compound layer in plan view.

7 . The connection structural body according to claim 1 , wherein:
the deposits are sheeted deposits, and a side surface of the bonding member is structured by the sheeted deposits that are piled over one another.

8 . The connection structural body according to claim 1 , wherein:
the deposits are granulated deposits, and a side surface of the bonding member is structured by the granulated deposits that are piled over one another.

9 . A semiconductor device, comprising:
a wiring substrate including a first connection terminal; a semiconductor element mounted on the wiring substrate and including a second connection terminal that faces the first connection terminal; and a bonding member bonding the first connection terminal and the second connection terminal, wherein the bonding member includes an intermetallic compound layer that is formed by a roughened-surface metal film, structured by deposits of metal piled over one another such that pores are formed, and a solder layer that is disposed in the pores.

Assignees

• Shinko Electric Ind Co

Inventors

• Aizawa Mitsuhiro

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/222

  Multilayered bumps, e.g. a coating on top and side surfaces of a bump core · CPC title