Semiconductor package

Patent metadata

Field	Value
Publication number	US-2022399296-A1
Application number	US-202217679444-A
Country	US
Kind code	A1
Filing date	Feb 24, 2022
Priority date	Jun 15, 2021
Publication date	Dec 15, 2022
Grant date	—

Abstract

A semiconductor package is provided. The semiconductor package includes a first structure with a first insulating layer and a connection pad which penetrates through the first insulating layer; and a second structure with a second insulating layer bonded to the first insulating layer and a pad structure provided in a recess portion of the second insulating layer. The pad structure is bonded to and wider than the connection pad. The pad structure includes: an electrode pad disposed on a bottom surface of the recess portion; a solder disposed on the electrode pad and bonded to the connection pad; and a conductive support disposed to surround a side surface of the solder on the electrode pad and bonded to the first insulating layer. A melting point of the conductive support is higher than a melting point of the solder.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a first structure comprising a first insulating layer and a connection pad which penetrates through the first insulating layer; and a second structure comprising a second insulating layer bonded to the first insulating layer and a pad structure provided in a recess portion of the second insulating layer, wherein the pad structure is bonded to the connection pad and is wider than the connection pad, wherein the pad structure comprises:
an electrode pad disposed on a bottom surface of the recess portion;
a solder disposed on the electrode pad and bonded to the connection pad; and
a conductive support disposed to surround a side surface of the solder on the electrode pad and bonded to the first insulating layer,
wherein a melting point of the conductive support is higher than a melting point of the solder.

2 . The semiconductor package of claim 1 , wherein the conductive support comprises any one or any combination of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au).

3 . The semiconductor package of claim 1 , wherein the solder is wider than the connection pad.

4 . The semiconductor package of claim 1 , wherein the connection pad overlaps the solder along a direction perpendicular to the first insulating layer.

5 . The semiconductor package of claim 1 , wherein the second insulating layer comprises any one or any combination of a solder resist and a photosensitive resin.

6 . The semiconductor package of claim 1 , wherein the pad structure comprises a plurality of pad structures, each of which has a width of 13 μm to 23 μm, and are spaced apart from each other by an interval of 10 μm or less.

7 . The semiconductor package of claim 1 , wherein an upper surface of the conductive support is substantially coplanar with an upper surface of the second insulating layer.

8 . The semiconductor package of claim 1 , wherein an upper surface of the solder is substantially coplanar with an upper surface of the second insulating layer.

9 . The semiconductor package of claim 1 , wherein the electrode pad and the pad structure have substantially similar widths.

10 . The semiconductor package of claim 1 , wherein the connection pad and the electrode pad are formed of substantially similar materials.

11 . The semiconductor package of claim 1 , wherein the second structure is wider than the first structure.

12 . A semiconductor package comprising:
a first semiconductor chip comprising a first insulating layer and a first pad structure which penetrates through the first insulating layer; and a second semiconductor chip comprising a second insulating layer bonded to the first insulating layer and a second pad structure provided in a recess portion of the second insulating layer, wherein the second pad structure is bonded to the first pad structure through the second insulating layer, wherein the second pad structure comprises:
an electrode pad disposed on a bottom surface of the recess portion;
a solder disposed on the electrode pad and bonded to the first pad structure; and
a conductive support disposed to surround a side surface of the solder on the electrode pad,
wherein a melting point of the conductive support is higher than a melting point of the solder.

13 . The semiconductor package of claim 12 , wherein the second semiconductor chip further comprises a body and a through-electrode that is electrically connected to the electrode pad and extends through the body.

14 . The semiconductor package of claim 13 , wherein the body is a silicon substrate.

15 . The semiconductor package of claim 12 , wherein the second semiconductor chip is an interposer substrate.

16 . A semiconductor package comprising:
a package substrate; an interposer substrate disposed on the package substrate; and at least one semiconductor chip disposed on the interposer substrate and comprising a lower insulating layer and a lower pad structure which penetrates through the lower insulating layer, wherein the interposer substrate comprises:
an upper insulating layer bonded to the lower insulating layer; and
an upper pad structure which is provided in a recess portion of the upper insulating layer and is bonded to the lower pad structure,
wherein the upper pad structure comprises:
an upper electrode pad disposed on a bottom surface of the recess portion of the upper insulating layer;
an upper solder disposed on the upper electrode pad and bonded to the lower pad structure; and
an upper conductive support disposed to surround a side surface of the upper solder on the upper electrode pad, and
wherein a melting point of the upper conductive support is higher than a melting point of the upper solder.

17 . The semiconductor package of claim 16 , wherein the upper solder is wider than the lower pad structure, and
wherein the lower pad structure and the upper pad structure are formed of substantially similar materials.

18 . The semiconductor package of claim 17 , wherein the lower pad structure overlaps the upper solder along a direction perpendicular to an upper surface of the package substrate.

19 . The semiconductor package of claim 16 , wherein the lower pad structure is provided in a recess portion of the lower insulating layer and comprises:
a lower electrode pad disposed on a bottom surface of the recess portion of the lower insulating layer; a lower solder disposed below the lower electrode pad and bonded to the upper solder; and a lower conductive support disposed to surround a side surface of the lower solder below the lower electrode pad, and bonded to the upper conductive support, and wherein a melting point of the lower conductive support is higher than a melting point of the lower solder.

20 . The semiconductor package of claim 19 , wherein
the upper insulating layer and the lower insulating layer are formed of substantially similar materials, the upper solder and the lower solder are formed of substantially similar materials, and the upper conductive support and the lower conductive support are formed of substantially similar materials.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Soonbum

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title