Semiconductor package including interposer

Patent metadata

Field	Value
Publication number	US-2020043853-A1
Application number	US-201916299340-A
Country	US
Kind code	A1
Filing date	Mar 12, 2019
Priority date	Jul 31, 2018
Publication date	Feb 6, 2020
Grant date	—

Abstract

Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a lower redistribution line structure comprising a plurality of lower insulating layers and a plurality of lower redistribution line patterns respectively on at least one of top surfaces and bottom surfaces of the plurality of lower insulating layers; a plurality of first connection pillars on at least portions of the plurality of lower redistribution line patterns, respectively; an interposer apart from the plurality of first connection pillars on the lower redistribution line structure and comprising an interposer substrate, a plurality of connection wiring patterns on a top surface of the interposer substrate, and a plurality of second connection pillars on at least portions of the plurality of connection wiring patterns, respectively; an upper redistribution line structure comprising at least one upper insulating layer and a plurality of upper redistribution line patterns on a top surface or a bottom surface of the at least one upper insulating layer and connected to the plurality of first connection pillars and the plurality of second connection pillars, respectively; and at least two semiconductor chips on the upper redistribution line structure, electrically connected to the plurality of upper redistribution line patterns, and apart from each other.

2 . The semiconductor package of claim 1 , wherein the lower redistribution line structure and the upper redistribution line structure each comprise a plurality of layers including circuit wires where the plurality of lower redistribution line patterns and the plurality of upper redistribution line patterns are,
wherein a number of layers included in the upper redistribution line structure is less than a number of layers included in the lower redistribution line structure.

3 . The semiconductor package of claim 1 , wherein a height of the plurality of first connection pillars is greater than a height of the plurality of second connection pillars.

4 . The semiconductor package of claim 1 , wherein a height of the plurality of first connection pillars is greater than a height of the interposer.

5 . The semiconductor package of claim 1 , wherein an uppermost portion of the plurality of first connection pillars and an uppermost portion of the plurality of second connection pillars are on a same level.

6 . The semiconductor package of claim 1 , wherein a lowermost portion of the plurality of first connection pillars is at a level lower than a bottom surface of the interposer.

7 . The semiconductor package of claim 1 , further comprising a filling insulating layer surrounding the plurality of first connection pillars and the interposer between the lower redistribution line structure and the upper redistribution line structure.

8 . The semiconductor package of claim 7 , wherein an uppermost portion of the plurality of first connection pillars, an uppermost portion of the plurality of second connection pillars, and a top surface of the filling insulating layer are coplanar.

9 . A semiconductor package comprising:
a package base substrate; a lower redistribution line structure on the package base substrate and comprising a plurality of lower redistribution line patterns; at least one interposer comprising a plurality of first connection pillars apart from each other on the lower redistribution line structure and connected to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns, respectively; an upper redistribution line structure comprising a plurality of upper redistribution line patterns connected to the plurality of first connection pillars and the plurality of connection wiring patterns, respectively, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips on the upper redistribution line structure apart from each other and electrically connected to the plurality of upper redistribution line patterns.

10 . The semiconductor package of claim 9 , configured to transmit signals between the at least two semiconductor chips via the upper redistribution line structure and the at least one interposer, and
configured to transmit signals between the at least two semiconductor chips and the package base substrate via the upper redistribution line structure, the plurality of first connection pillars, and the lower redistribution line structure.

11 . The semiconductor package of claim 9 , wherein a minimum pitch of the plurality of upper redistribution line patterns is greater than a minimum pitch of the plurality of connection wiring patterns.

12 . The semiconductor package of claim 9 , wherein a width and a thickness of the plurality of upper redistribution line patterns are greater than a width and a thickness of the plurality of connection wiring patterns.

13 . The semiconductor package of claim 9 , wherein the at least two semiconductor chips comprise a main semiconductor chip and a plurality of sub-semiconductor chips,
wherein the at least one interposer comprises a plurality of sub-interposers that overlap a portion of the main semiconductor chip and a portion of each of the plurality of sub-semiconductor chips to electrically interconnect the main semiconductor chip to each of the plurality of sub-semiconductor chips.

14 . The semiconductor package of claim 9 , wherein the at least two semiconductor chips comprise a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip,
wherein the at least one interposer comprises a first sub-interposer that overlaps a portion of the first semiconductor chip and a portion of the second semiconductor chip to electrically connect the first semiconductor chip to the second semiconductor chip, and a second sub-interposer that overlaps another portion of the second semiconductor chip and a portion of the third semiconductor chip to electrically connect the second semiconductor chip to the third semiconductor chip.

15 . The semiconductor package of claim 9 , further comprising a heat emitting member contacting a top surface of the at least two semiconductor chips.

16 . The semiconductor package of claim 15 , wherein the heat emitting member surrounds the at least two semiconductor chips by contacting a top surface of the package base substrate.

17 . The semiconductor package of claim 9 , wherein the at least two semiconductor chips comprise a first semiconductor chip and a second semiconductor chip.
wherein the at least one interposer each comprises a first sub-interposer that overlaps a portion of the first semiconductor chip and a portion of the second semiconductor chip to electrically connect the first semiconductor chip to the second semiconductor chip, and a second sub-interposer that overlaps the other portion of the first semiconductor chip and the other portion of the second semiconductor chip.

18 . A semiconductor package comprising:
a lower redistribution line structure comprising a plurality of lower redistribution line patterns; an interposer on the lower redistribution line structure, the interposer comprising a plurality of first connection pillars connected to the plurality of lower redistribution line patterns, an interposer substrate, a plurality of connection wiring patterns on the interposer substrate, and a plurality of second connection pillars on the plurality of connection wiring patterns; an upper redistribution line structure comprising a plurality of upper redistribution line patterns electrically connected

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jong-Youn
• Lee Seok-Hyun

Classifications

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title