Semiconductor package

Patent metadata

Field	Value
Publication number	US-2022037261-A1
Application number	US-202117349174-A
Country	US
Kind code	A1
Filing date	Jun 16, 2021
Priority date	Jul 31, 2020
Publication date	Feb 3, 2022
Grant date	—

Abstract

A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer, wherein each of the redistribution patterns comprises a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion, the via portion, the pad portion, and the line portion are connected to each other to form a single object, a level of a bottom surface of the pad portion is lower than a level of a bottom surface of the line portion, and a width of the line portion has a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

2 . The semiconductor package of claim 1 , wherein a difference in the level between the bottom surface of the pad portion and the bottom surface of the line portion ranges from 0.2 μm to 0.5 μm.

3 . The semiconductor package of claim 1 , wherein a diameter of the pad portion has a largest value at a level between a top surface of the pad portion and the bottom surface of the pad portion.

4 . The semiconductor package of claim 1 , wherein a difference between the largest value of the width of the line portion and a width of the top surface of the line portion is greater than 0 nm and is smaller than 300 nm.

5 . The semiconductor package of claim 1 , wherein each of the redistribution patterns comprises:
a metal pattern in the insulating layer; and a seed/barrier pattern between a bottom surface of the metal pattern and the insulating layer and between a side surface of the metal pattern and the insulating layer.

6 . The semiconductor package of claim 5 , wherein an upper portion of the metal pattern has a groove portion near the seed/barrier pattern.

7 . The semiconductor package of claim 6 , wherein the groove portion has a depth greater than 0 nm and smaller than 300 nm.

8 . The semiconductor package of claim 1 , wherein a diameter of the pad portion is 1.5 times larger than the width of the line portion.

9 . The semiconductor package of claim 1 , wherein
each of the redistribution patterns further comprises a second pad portion connected to an end portion of the line portion such that the second pad portion and the line portion form a single object, and a level of a bottom surface of the second pad portion is lower than the level of the bottom surface of the line portion.

10 . A semiconductor package comprising:
a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer, wherein each of the redistribution patterns comprises a via portion, a pad portion, and a line portion that are connected to each other to form a single object, the pad portion vertically overlaps the via portion, the line portion extends from the pad portion, a level of a bottom surface of the pad portion is lower than a level of a bottom surface of the line portion, a side surface of the via portion has a linear shape, and a side surface of the pad portion has a rounded shape.

11 . The semiconductor package of claim 10 , wherein the side surface of the via portion comprises:
a lower sidewall portion having a first slope; and an upper sidewall portion having a second slope, wherein the upper sidewall portion is connected to the bottom surface of the pad portion, and an absolute value of the first slope is greater than an absolute value of the second slope.

12 . The semiconductor package of claim 11 , wherein an angle of the first slope is smaller than 90°.

13 . The semiconductor package of claim 10 , wherein the bottom surface of the pad portion and the side surface of the via portion are connected to form an edge portion having a rounded shape.

14 . The semiconductor package of claim 10 , wherein each of the redistribution patterns comprises:
a metal pattern in the insulating layer; and a seed/barrier pattern between a bottom surface of the metal pattern and the insulating layer and between a side surface of the metal pattern and the insulating layer.

15 . The semiconductor package of claim 10 , wherein an angle between the side surface of the via portion and a bottom surface of the via portion is greater than 95°.

16 . A semiconductor package comprising:
a lower redistribution substrate including an insulating layer and first redistribution patterns in the insulating layer; a first semiconductor chip on the lower redistribution substrate, the first semiconductor chip comprising chip pads; first connection terminals being between and connecting the lower redistribution substrate and the chip pads of the first semiconductor chip; a mold layer on the lower redistribution substrate to cover the first semiconductor chip; metal pillars around the first semiconductor chip to penetrate the mold layer and connected to the lower redistribution substrate; and an upper redistribution substrate on the mold layer, the upper redistribution substrate comprising an upper insulating layer and an upper redistribution pattern on the upper insulating layer, wherein each of the first redistribution patterns comprises a first via portion, a first pad portion, and a first line portion that are connected to each other to form a single object, the first pad portion vertically overlaps with the first via portion, the first line portion extends from the first pad portion, and a level of a bottom surface of the first line portion is lowered with increasing a distance from a center portion of the first line portion in an outward direction.

17 . The semiconductor package of claim 16 , wherein
the first line portion has a rounded edge portion between the bottom surface of the first line portion and a side surface of the first line portion, and the rounded edge portion has a curvature radius of 0.3 μm or larger.

18 . The semiconductor package of claim 16 , wherein a difference between a level of a center portion of the bottom surface of the first line portion and a level of an edge portion of the bottom surface of the first line portion is greater than 0 nm and is smaller than 300 nm.

19 . The semiconductor package of claim 16 , wherein
the lower redistribution substrate further comprises second redistribution patterns in the insulating layer, the first redistribution patterns each have a smallest width of a first width at a top surface or a bottom surface thereof, the second redistribution patterns each have a smallest width of a second width at a top surface or a bottom surface thereof, the second width is larger than the first width, the second redistribution patterns comprises a second line portion, and a level of a bottom surface of the second line portion is lower than the level of the bottom surface of the first line portion.

20 . The semiconductor package of claim 19 , wherein a top surface of the first line portion and a top surface of the second line portion are at a same level.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Ju-Il
• Kang Gyuho
• Kang Un-Byoung
• Kim Byeongchan
• Park Junyoung
• Lee Jongho
• Hwang Hyunsu

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W90/00

  Package configurations · CPC title