Solder thermal interface material (stim) with dopant

Patent metadata

Field	Value
Publication number	US-2020357764-A1
Application number	US-201916406593-A
Country	US
Kind code	A1
Filing date	May 8, 2019
Priority date	May 8, 2019
Publication date	Nov 12, 2020
Grant date	—

Abstract

Embodiments may relate to a microelectronic package comprising that includes a solder thermal interface material (STIM). The STIM may include indium and a dopant material which may provide a number of benefits to the STIM. The STIM may physically and thermally couple a die and an integrated heat spreader (IHS). Other embodiments may be described or claimed.

First claim

1 . A microelectronic package comprising:
a die; a solder thermal interface material (STIM), wherein the STIM includes:
indium; and
greater than 0% and less than 5% by weight of another material; and
an integrated heat spreader (IHS), wherein the STIM is between the IHS and the die.

2 . The microelectronic package of claim 1 , wherein the material is to improve wettability of the indium to its own intermetallic.

3 . The microelectronic package of claim 2 , wherein the material includes bismuth or silver.

4 . The microelectronic package of claim 1 , wherein the material is to reduce a tendency of the STIM to deform under stress.

5 . The microelectronic package of claim 4 , wherein the material includes bismuth.

6 . The microelectronic package of claim 1 , wherein the material is to inhibit intermetallic growth of the STIM during thermal cycling of the microelectronic package.

7 . The microelectronic package of claim 6 , wherein the material includes cobalt or a combination of cerium and oxygen.

8 . The microelectronic package of claim 6 , wherein the material is to act as a diffusion barrier for the intermetallic growth.

9 . A microelectronic package comprising:
a die coupled with a package substrate; and a solder thermal interface material (STIM) physically and thermally coupled with the die, wherein the STIM includes: indium; and a dopant material that includes silver, bismuth, cobalt, or cerium oxide (CeO2).

10 . The microelectronic package of claim 9 , further comprising an integrated heat spreader (IHS) physically and thermally coupled with the STIM.

11 . The microelectronic package of claim 9 , wherein the STIM includes less than 5% by weight of the dopant material.

12 . The microelectronic package of claim 9 , wherein the bismuth is to improve wettability of the indium to its own intermetallic or reduce a tendency of the STIM to deform under stress.

13 . The microelectronic package of claim 9 , wherein the silver is to improve wettability of the indium to its own intermetallic.

14 . The microelectronic package of claim 9 , wherein the cobalt is to inhibit intermetallic growth of the STIM during thermal cycling of the microelectronic package or to act as a diffusion barrier.

15 . The microelectronic package of claim 9 , wherein the CeO2 is to inhibit intermetallic growth of the STIM during thermal cycling of the microelectronic package.

16 . A method of forming a microelectronic package that includes a solder thermal interface material (STIM), wherein the method comprises:
positioning a die; placing the STIM on a face of the die, wherein the STIM includes indium and another material; and placing an integrated heat spreader (IHS) on the STIM such that the STIM is positioned between the die and the IHS.

17 . The method of claim 16 , wherein the STIM includes less than 5% by weight of the material.

18 . The method of claim 16 , wherein the material includes silver, bismuth, cobalt, or a combination of cerium and oxygen.

19 . The method of claim 16 , wherein placing the STIM on the face of the die includes placing a preform that includes the STIM on the face of the die, and wherein the material is intermixed with the indium within the preform.

20 . The method of claim 16 , wherein placing the STIM on the face of the die includes placing a preform that includes the STIM on the face of the die, and wherein the material is arranged as a layer of the preform that is adjacent to a layer of the indium.

Assignees

• Intel Corp

Inventors

• Das Mahapatra Susmriti
• Falola Bamidele Daniel
• Saha Amitesh
• Li Peng

Classifications

• H10W72/07355

  changes in materials · CPC title

• H10W72/3528

  Intermetallic compounds · CPC title

• H10W72/353

  not comprising solid metals or solid metalloids, e.g. ceramics · CPC title

• H10W72/352

  comprising metals or metalloids, e.g. solders · CPC title

• H10W40/258

  Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title