Three-dimensional memory devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-2024107761-A1
Application number	US-202217968595-A
Country	US
Kind code	A1
Filing date	Oct 18, 2022
Priority date	Sep 23, 2022
Publication date	Mar 28, 2024
Grant date	—

Abstract

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

First claim

What is claimed is:

1 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a stack structure comprising interleaved first dielectric layers and second dielectric layers; forming channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure; replacing all the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure with conductive layers; and forming word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

2 . The method of claim 1 , further comprising forming dummy channel structures extending through the first dielectric layers and the second dielectric layers in the second region of the stack structure in a same process of forming the channel structures.

3 . The method of claim 1 , wherein replacing comprises forming a slit extending through the first dielectric layers and the second dielectric layers and across the first region and the second region of the stack structure before forming the word line pick-up structures.

4 . The method of claim 3 , wherein replacing further comprises:
covering the slit in the second region of the stack structure; removing all the second dielectric layers in the first region of the stack structure through the slit in the first region of the stack structure; opening the slit in the second region of the stack structure; removing the parts of the second dielectric layers in the second region of the stack structure through the slit in the second region of the stack structure; and depositing the conductive layers through the slit in the first region and the second region of the stack structure.

5 . The method of claim 3 , wherein replacing further comprises:
covering the slit in the first region of the stack structure; removing the parts the second dielectric layers in the second region of the stack structure through the slit in the second region of the stack structure; opening the slit in the first region of the stack structure; covering the slit in the second region of the stack structure; removing all the second dielectric layers in the first region of the stack structure through the slit in the first region of the stack structure; opening the slit in the second region of the stack structure; and depositing the conductive layers through the slit in the first region and the second region of the stack structure.

6 . The method of claim 3 , further comprising forming a first spacer in the slit before forming the word line pick-up structures.

7 . The method of claim 1 , wherein forming the word line pick-up structures comprises:
forming word line pick-up openings extending through the first dielectric layers and the remainders of the second dielectric layers in the second region of the stack structure at different depths to expose the remainders of the second dielectric layers in the second regions of the stack structure, respectively; replacing, through the word line pick-up openings, parts of the remainders of the second dielectric layers in the second region of the stack structure with interconnect lines, respectively, such that the interconnect lines are in contact with the conductive layers, respectively, in the second region of the stack structure; and forming vertical contacts in the word line pick-up openings in contact with the interconnect lines, respectively.

8 . The method of claim 7 , wherein forming the word line pick-up structures further comprises:
forming a second spacer on sidewalls and a bottom of each of the word line pick-up openings; removing the second spacer on the bottom of the word line pick-up opening to expose the respective part of the remainder of the second dielectric layer; and forming a filler in the word line pick-up opening after forming the respective vertical contact.

9 . The method of claim 8 , wherein replacing the parts of the second dielectric layers with the interconnect lines comprises:
etching the exposed part of the remainder of the second dielectric layer through the word line pick-up opening to expose the respective conductive layer in the second region of the stack structure; and depositing the respective interconnect line through the word line pick-up opening to be in contact with the exposed respective conductive layer in the second region of the stack structure.

10 . The method of claim 9 , wherein
replacing all the second dielectric layers and the parts of the second dielectric layers with the conductive layers comprises depositing high dielectric constant (high-k) gate dielectric layers, such that the conductive layers are surrounded by the high-k gate dielectric layers, respectively; and replacing the parts of the second dielectric layers with the interconnect lines further comprises:
etching the exposed part of the remainder of the second dielectric layer to expose the respective high-k gate dielectric layer;
etching the exposed high-k gate dielectric layer to expose the respective conductive layer; and
depositing the respective interconnect line to be in contact with the exposed respective conductive layer.

11 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a stack structure comprising interleaved first dielectric layers and second dielectric layers; forming channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure; forming word line pick-up structures extending through the first dielectric layers and the second dielectric layers in a second region of the stack structure at different depths; and replacing all the second dielectric layers in the first region and parts of the second dielectric layers in the second region of the stack structure with conductive layers, such that the conductive layers are electrically connected to the word line pick-up structures, respectively, in the second region of the stack structure.

12 . The method of claim 11 , further comprising forming dummy channel structures extending through the first dielectric layers and the second dielectric layers in the second region of the stack structure in a same process of forming the channel structures.

13 . The method of claim 11 , wherein forming the word line pick-up structures comprises:
forming word line pick-up openings extending through the first dielectric layers and the second dielectric layers in the second region of the stack structure at different depths to expose the second dielectric layers in the second regions of the stack structure, respectively; replacing, through the word line pick-up openings, parts of the second dielectric layers in the second region of the stack structure with interconnect lines, respectively; and forming vertical contacts in the word line pick-up openings in contact with the interconnect lines, respectively.

14 . The method of claim 13 , wherein forming the word line pick-up structures further comprises:
forming a second spacer on sidewalls and a bottom of each of the word line pick-up openings; removing the second spacer on the bottom of the word line pick-up opening to expose the respective part of the second dielectric layer; and forming a filler in the word line pick-up opening after forming t

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wang Di
• Zhang Zhong
• Zhou Wenxi
• Xia Zhiliang
• Huo Zongliang
• Xie Wei

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50 Primary

  characterised by the boundary region between the core and peripheral circuit regions · CPC title