Semiconductor devices and data storage systems including the same

Patent metadata

Field	Value
Publication number	US-2023080606-A1
Application number	US-202217852812-A
Country	US
Kind code	A1
Filing date	Jun 29, 2022
Priority date	Sep 10, 2021
Publication date	Mar 16, 2023
Grant date	—

Abstract

A semiconductor device may include: a semiconductor substrate; a peripheral circuit structure on the semiconductor substrate; a plate pattern on the peripheral circuit structure and having a gap; and a stack structure on the plate pattern and including a first stack region and a second stack region. The first stack region may include gate electrodes stacked in a vertical direction perpendicular to an upper surface of the semiconductor substrate, and the second stack region may include both a conductor stack region including conductive layers stacked in the vertical direction and an insulator stack region including molded insulating layers at substantially the same height level as the conductive layers. The semiconductor device may also include vertical memory structure that extends through the first stack region; and source contact plugs electrically connected to at least one of the conductive layers of the conductor stack region and contacting the plate pattern.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a semiconductor substrate; a peripheral circuit structure on the semiconductor substrate; a plate pattern having a gap and on the peripheral circuit structure; a stack structure on the plate pattern and including a first stack region and a second stack region spaced apart from the first stack region, wherein the first stack region includes gate electrodes stacked in a vertical direction that is perpendicular to an upper surface of the semiconductor substrate, wherein the second stack region includes a conductor stack region including conductive layers stacked in the vertical direction, and wherein the second stack region includes an insulator stack region including molded insulating layers at substantially the same height level as the conductive layers; a vertical memory structure that extends through the first stack region; and source contact plugs electrically connected to at least one of the conductive layers of the conductor stack region and in contact with the plate pattern.

2 . The semiconductor device of claim 1 , further comprising:
a bitline on the stack structure; and a first peripheral contact plug that extends through at least the insulator stack region and is electrically connected to a first peripheral pad of the peripheral circuit structure; a first bitline connection plug that electrically connects the vertical memory structure and the bitline to each other; and a second bitline connection plug that electrically connects the first peripheral contact plug and the bitline to each other, wherein: the gap has a line shape or a bar shape extending in a first direction that is parallel to the upper surface of the semiconductor substrate; and the bitline has a line shape or a bar shape extending in a second direction that is parallel to the upper surface of the semiconductor substrate and is perpendicular to the first direction.

3 . The semiconductor device of claim 2 , further comprising:
a first source connection line on the stack structure; and a source connection pattern, wherein the source contact plugs include at least one first source contact plug that overlap the first source connection line, and second source contact plugs that do not overlap the first source connection line; wherein at least one of the second source contact plugs overlaps the bitline; wherein the source connection pattern electrically connects the first source connection line with the first source contact plug; wherein the first source connection line has a line shape extending in the second direction; and wherein a width of the first source connection line is greater than a width of the bitline.

4 . The semiconductor device of claim 3 , wherein:
the width of the first source connection line is about three times to ten times greater than the width of the bitline.

5 . The semiconductor device of claim 3 , wherein:
at least one of the source contact plugs is between the insulator stack region and the conductor stack region; and the source connection pattern electrically connects the first source contact plug with the first source connection line.

6 . The semiconductor device of claim 3 , further comprising:
first patterns contacting at least an uppermost conductive layer among the conductive layers of the conductor stack region; and second patterns electrically connecting the first patterns and the source contact plugs to each other, wherein the source contact plugs are electrically connected to at least one of the conductive layers through the first and second patterns; and wherein the source connection pattern is in contact with and electrically connected to a second pattern, electrically connected to the first source contact plug, among the second patterns.

7 . The semiconductor device of claim 3 , further comprising:
external source contact plugs spaced apart from the first and second stack regions and contacting the plate pattern; and a second source connection line electrically connecting the external source contact plugs to each other on the external source contact plugs, wherein the source contact plugs and the external source contact plugs have upper surfaces o an equal distance from the upper surface of the semiconductor substrate; and wherein the second source connection line and the first source connection line are an equal distance from the upper surface of the semiconductor substrate.

8 . The semiconductor device of claim 7 , further comprising:
a source peripheral contact plug electrically connected to a source pad of the peripheral circuit structure and having an upper surface having a level farther from the upper surface of the semiconductor substrate than a level of an uppermost gate electrode among the gate electrodes is from the upper surface of the semiconductor substrate; a first upper interconnection structure electrically connecting the first source connection line with the second source connection line; and a second upper interconnection structure electrically connecting the first upper interconnection structure with the source peripheral contact plug.

9 . The semiconductor device of claim 1 , further comprising:
separation structures that extend through the stack structure, wherein, in a plan view, the separation structures include a first main separation structure and a second main separation structure opposing each other with the gap interposed therebetween; wherein the second stack region is between the first main separation structure and the second main separation structure; and wherein the conductor stack region of the second stack region comprises:
a first stack portion between the first main separation structure and the insulator stack region;
a second stack portion between the second main separation structure and the insulator stack region; and
a third stack portion connecting the first stack portion with the second stack portion.

10 . The semiconductor device of claim 9 , wherein:
the gap has a line shape or a bar shape that extends in a first direction that is parallel to the upper surface of the semiconductor substrate; and when viewed in a plan view from a height level on which one of the conductive layers is arranged, the third stack portion includes portions convex in a direction toward the insulator stack region.

11 . The semiconductor device of claim 9 , wherein:
when viewed in a plan view from a height level of one of the conductive layers, a first boundary between the first stack portion and the insulator stack region and a second boundary between the second stack portion and the insulator stack region are in a form of a line extending in a first direction that is parallel to the upper surface of the semiconductor substrate; and a third boundary between the third stack portion and the insulator stack region extends in a second direction that is parallel to the upper surface of the semiconductor substrate and perpendicular to the first direction.

12 . The semiconductor device of claim 9 , further comprising:
a source connection line on the stack structure, wherein the source contact plugs include first side source contact plugs that extend through the first stack portion, second side source contact plugs that extend through the second stack portion, and third side source contact plugs that extend through the third stack portion; and wherein the source connection line overlaps at least one of the first side source contact plugs and overlaps at least one of the second side source contact plugs.

13 . The semiconductor device of claim 1 , wherein:
a first of the source contact

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Seungmin
• Kim Junhyoung
• Kim Kangmin
• Lim Joonsung

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10B43/50 Primary

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/40 Primary

  characterised by the peripheral circuit region · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title