Multi-chip package and method of providing die-to-die interconnects in same

Patent metadata

Field	Value
Publication number	US-2023016326-A1
Application number	US-202217956761-A
Country	US
Kind code	A1
Filing date	Sep 29, 2022
Priority date	Jun 24, 2009
Publication date	Jan 19, 2023
Grant date	—

Abstract

A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

First claim

What is claimed is:

1 . A multi-chip package, comprising:
a substrate; a bridge on the substrate, the bridge having a top side opposite a bottom side, and the bridge having a first sidewall and a second sidewall between the top side and the bottom side, the first sidewall lateral opposite the second sidewall; an underfill material in contact with at least one of the first sidewall or the second sidewall of the bridge; a first die over a first portion of the top side of the bridge and over the substrate, the first die coupled to the first portion of the top side of the bridge by a first plurality of interconnect structures, the first plurality of interconnect structures having a first pitch, and the first die coupled to the substrate by a second plurality of interconnect structures, the second plurality of interconnect structures having a second pitch greater than the first pitch; and a second die over a second portion of the top side of the bridge and over the substrate, the second die coupled to the second portion of the top side of the bridge by a third plurality of interconnect structures, the third plurality of interconnect structures having the first pitch.

2 . The multi-chip package of claim 1 , wherein the bridge is surrounded by a cavity of the substrate.

3 . The multi-chip package of claim 1 , wherein the second die is coupled to the substrate by a fourth plurality of interconnect structures, the fourth plurality of interconnect structures having the second pitch.

4 . The multi-chip package of claim 1 , wherein the bridge comprises silicon.

5 . The multi-chip package of claim 1 , wherein the first die and the second die are flip-chip attached to the bridge.

6 . The multi-chip package of claim 1 , wherein the bridge does not include a through silicon via.

7 . A method of fabricating a multi-chip package, the method comprising:
providing a die on a substrate, the die having a first side opposite a second side, and the die having a first sidewall and a second sidewall between the first side and the second side, the first sidewall lateral opposite the second sidewall; forming an underfill material in contact with both the first sidewall and the second sidewall of the die; providing a first chip over a first portion of the first side of the die and over the substrate, the first chip coupled to the first portion of the first side of the die by a first plurality of interconnect structures, the first plurality of interconnect structures having a first pitch, and the first chip coupled to the substrate by a second plurality of interconnect structures, the second plurality of interconnect structures having a second pitch greater than the first pitch; and providing a second chip over a second portion of the first side of the die and over the substrate, the second chip coupled to the second portion of the first side of the die by a third plurality of interconnect structures, the third plurality of interconnect structures having the first pitch.

8 . The method of claim 7 , wherein the die is surrounded by a cavity of the substrate.

9 . The method of claim 7 , wherein the second chip is coupled to the substrate by a fourth plurality of interconnect structures, the fourth plurality of interconnect structures having the second pitch.

10 . The method of claim 7 , wherein the die comprises silicon.

11 . The method of claim 7 , wherein the first chip and the second chip are flip-chip attached to the die.

12 . The method of claim 7 , wherein the die does not include a through silicon via.

13 . A multi-chip package, comprising:
a substrate; a bridge in the substrate, the bridge having a top side opposite a bottom side, and the bridge having a first sidewall and a second sidewall between the top side and the bottom side, the first sidewall lateral opposite the second sidewall; an underfill material in contact with at least one of the first sidewall or the second sidewall of the bridge; a first die over a first portion of the top side of the bridge and over the substrate, the first die coupled to the first portion of the top side of the bridge by a first plurality of interconnect structures, the first plurality of interconnect structures having a first pitch, and the first die coupled to the substrate by a second plurality of interconnect structures, the second plurality of interconnect structures having a second pitch greater than the first pitch; and a second die over a second portion of the top side of the bridge and over the substrate, the second die coupled to the second portion of the top side of the bridge by a third plurality of interconnect structures, the third plurality of interconnect structures having the first pitch.

14 . The multi-chip package of claim 13 , wherein the bridge is in a cavity of the substrate.

15 . The multi-chip package of claim 13 , wherein the second die is coupled to the substrate by a fourth plurality of interconnect structures, the fourth plurality of interconnect structures having the second pitch.

16 . The multi-chip package of claim 13 , wherein the bridge comprises silicon.

17 . The multi-chip package of claim 13 , wherein the first die and the second die are flip-chip attached to the bridge.

18 . The multi-chip package of claim 13 , wherein the bridge does not include a through silicon via.

19 . A method of fabricating a multi-chip package, the method comprising:
providing a die in a substrate, the die having a first side opposite a second side, and the die having a first sidewall and a second sidewall between the first side and the second side, the first sidewall lateral opposite the second sidewall; forming an underfill material in contact with both the first sidewall and the second sidewall of the die; providing a first chip over a first portion of the first side of the die and over the substrate, the first chip coupled to the first portion of the first side of the die by a first plurality of interconnect structures, the first plurality of interconnect structures having a first pitch, and the first chip coupled to the substrate by a second plurality of interconnect structures, the second plurality of interconnect structures having a second pitch greater than the first pitch; and providing a second chip over a second portion of the first side of the die and over the substrate, the second chip coupled to the second portion of the first side of the die by a third plurality of interconnect structures, the third plurality of interconnect structures having the first pitch.

20 . The method of claim 19 , wherein the die is in a cavity of the substrate.

21 . The method of claim 19 , wherein the second chip is coupled to the substrate by a fourth plurality of interconnect structures, the fourth plurality of interconnect structures having the second pitch.

22 . The method of claim 19 , wherein the die comprises silicon.

23 . The method of claim 19 , wherein the first chip and the second chip are flip-chip attached to the die.

24 . The method of claim 19 , wherein the die does not include a through silicon via.

Assignees

• Intel Corp

Inventors

• Braunisch Henning M
• Chiu Chia-Pin
• Aleksov Aleksander
• Au Hinmeng
• Lotz Stefanie M
• Swan Johanna M
• Sharan Sujit

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title