High-side gate over-voltage stress testing

Patent metadata

Field	Value
Publication number	US-2022260627-A1
Application number	US-202217739911-A
Country	US
Kind code	A1
Filing date	May 9, 2022
Priority date	Dec 22, 2016
Publication date	Aug 18, 2022
Grant date	—

Abstract

A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.

First claim

What is claimed is:

1 . A circuit comprising:
a substrate having a probe pad, a supply input, and an electrical ground input; a driver circuit having an output; a first transistor having a first control terminal coupled to the output of the driver circuit and having another terminal coupled to the supply input; and probe pad coupling circuitry including:
a second transistor having a second control terminal and first and second terminals, the first terminal coupled to the output of the driver circuit and to the first control terminal, the second terminal coupled to the probe pad; and
a diode having respective first and second terminals, the first terminal of the diode coupled to the second terminal of the second transistor and to the probe pad, the second terminal of the diode coupled to the electrical ground input.

2 . The circuit of claim 1 , wherein the first and second transistors are field effect transistors.

3 . The circuit of claim 1 , wherein the first and second transistors are n-type metal-oxide-semiconductor field-effect transistors.

4 . The circuit of claim 1 , wherein the probe pad coupling circuitry includes a resistor having respective first and second terminals, the first terminal of the resistor coupled to the second control terminal, the second terminal of the resistor coupled to the electrical ground input and to the second terminal of the diode.

5 . The circuit of claim 1 , wherein the substrate has a second probe pad coupled to the second control terminal.

6 . The circuit of claim 1 , wherein the substrate includes a controller having a respective output coupled to the second control terminal.

7 . The circuit of claim 1 , wherein the first terminal of the diode is an anode, and the second terminal is a cathode.

8 . A circuit comprising:
a substrate having a probe pad, a supply input, and an electrical ground input; a driver circuit having an output; a field effect transistor (FET) having a gate coupled to the output of the driver circuit and having another terminal coupled to the supply input; and probe pad coupling circuitry including:
a transistor having a control terminal and first and second terminals, the first terminal coupled to the output of the driver circuit and to the gate, the second terminal coupled to the probe pad;
a diode having respective first and second terminals, the first terminal of the diode coupled to the second terminal of the transistor and to the probe pad, the second terminal of the diode coupled to the electrical ground input; and
a resistor having respective first and second terminals, the first terminal of the resistor coupled to the control terminal, the second terminal of the resistor coupled to the electrical ground input and to the second terminal of the diode.

9 . The circuit of claim 8 , wherein the FET is a first FET, and the transistor is a second FET.

10 . The circuit of claim 8 , wherein the FET and the transistor are n-type metal-oxide-semiconductor field-effect transistors.

11 . The circuit of claim 8 , wherein the substrate has a second probe pad coupled to the control terminal.

12 . The circuit of claim 8 , wherein the substrate includes a controller having a respective output coupled to the control terminal.

13 . The circuit of claim 1 , wherein the first terminal of the diode is an anode, and the second terminal is a cathode.

14 . A system comprising:
a test instrument having a probe; a substrate having a probe pad electrically coupled to the probe, having a supply input, and having an electrical ground input, the substrate including;
a driver circuit having an output;
a first field effect transistor (FET) having a first gate coupled to the output of the driver circuit and having another terminal coupled to the supply input; and
probe pad coupling circuitry including:
a second FET having a second gate and first and second terminals, the first terminal coupled to the output of the driver circuit and to the first gate, the second terminal coupled to the probe pad;
a diode having respective first and second terminals, the first terminal of the diode coupled to the second terminal of the second FET and to the probe pad, the second terminal of the diode coupled to the electrical ground input.

15 . The system of claim 14 , wherein the first and second FETs are n-type metal-oxide-semiconductor field-effect transistors.

16 . The system of claim 14 , wherein the probe pad coupling circuitry includes a resistor having respective first and second terminals, the first terminal of the resistor coupled to the second gate, the second terminal of the resistor coupled to the electrical ground input and to the second terminal of the diode.

17 . The system of claim 14 , wherein the substrate has a second probe pad coupled to the second gate, and the system further comprising a second test instrument having a respective probe electrically coupled to the second probe pad.

18 . The system of claim 14 , wherein the substrate includes a controller having a respective output coupled to the second gate.

19 . The system of claim 14 , wherein the first terminal of the diode is an anode, and the second terminal is a cathode.

Assignees

• Texas Instruments Inc

Inventors

• Gonzalez Diaz Sigfredo E
• Amey Benjamin Lee
• Teterud Patrick Michael
• Nguyen Hung

Classifications

• G01R31/2623 Primary

  for measuring break-down voltage therefor · CPC title