Devices under test

Patent metadata

Field	Value
Publication number	US-9778313-B2
Application number	US-201414479940-A
Country	US
Kind code	B2
Filing date	Sep 8, 2014
Priority date	Sep 8, 2014
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A system can include a plurality of device under test (DUT) cells. Each DUT cell can include a DUT and a plurality of switches configured to control a flow of current to the DUT. The system can further include a controller configured to execute a plurality of test to the plurality of DUTs in the plurality of DUT cells. Each of the plurality of tests comprises applying a measurement condition to a given DUT of the plurality of DUTs and concurrently applying a stress condition to the remaining DUTs of the plurality of DUTs, wherein the plurality of tests can provide measurements sufficient to determine a bias thermal instability and a time dependent dielectric breakdown of the given DUT.

First claim

What is claimed is:

1. A system comprising:
a plurality of DUTs (device under test) and a plurality of switches configured to control a flow of current to the plurality of DUTs, wherein each of the plurality of the DUTs comprises an electronic component; and
a controller configured to execute a plurality of tests on the plurality of DUTs, wherein each of the plurality of tests comprises applying a measurement condition to a given DUT of the plurality of DUTs and concurrently applying a stress condition to the remaining DUTs of the plurality of DUTs, wherein the plurality of tests provide measurements sufficient to determine a bias thermal instability and a time dependent dielectric breakdown of the given DUT; and wherein the stress condition of the remaining DUTs of the plurality of DUTs is configured to shunt leakage current away from the given DUT.

2. The system of claim 1 , wherein each of the plurality of DUTs comprises a semiconductor device.

3. The system of claim 2 , wherein each of the plurality of DUTs comprises a p-channel metal-oxide-semiconductor field effect transistor (MOSFET).

4. The system of claim 2 , wherein each of the DUTs in the plurality of DUTs comprise an n-channel metal-oxide-semiconductor field effect transistor (MOSFET).

5. The system of claim 1 , wherein the plurality of tests further measure a random telegraph noise of the given DUT.

6. The system of claim 1 , wherein the stress condition applies a voltage to each of the remaining plurality of DUTs that is higher or lower than a rated voltage of each of the plurality of DUTs.

7. The system of claim 1 , wherein the plurality of tests further measure a process variation of the given DUT.

8. A method comprising:
applying a stress condition to a plurality of devices under test (DUTs);
applying a measurement condition to a given DUT in the plurality of DUTs while concurrently maintaining the stress condition on a remaining DUTs in the plurality of DUTs, wherein applying the stress condition is configured to shunt leakage current of the remaining DUTs away from the given DUT;
repeating the applying for each DUT in the plurality of DUTs; and
determining degradation parameters of each DUT in the plurality of DUTs.

9. The method of claim 8 , wherein the operational characteristics for the plurality of DUTs comprise a bias temperature instability (BTI) and a temperature dependent dielectric breakdown (TDDB).

10. The method of claim 9 , wherein the BTI and the TDDB are based on signals measured during separate applications of the measurement condition.

11. The method of claim 8 , further comprising:
determining that a gate current for a particular DUT of the plurality of DUTs is at or above a threshold level; and
applying a disconnect condition to the particular DUT in response to the determining.

12. The method of claim 8 , wherein the stress condition applies a stress voltage to a terminal of each of the plurality of DUTs, wherein the stress voltage is higher or lower than a voltage rating of each of the plurality of DUTs.

13. A method comprising:
applying a first test condition to a plurality of DUTs, wherein the first test condition comprises:
applying a first stress condition to each of the plurality of DUTs, wherein the first stress condition is configured to apply a stress voltage to each of the plurality of DUTs that is higher or lower than a rated voltage of each of the plurality of DUTs;
applying a first measurement condition to a given DUT of the plurality of DUTs while maintaining the first stress condition at each of the remaining DUTs of the plurality of DUTs;
measuring a drain current at the given DUT; and
repeating the applying of the first stress condition and the first measurement condition for each DUT in the plurality of DUTs; and

applying a second test condition to the plurality of DUTs, wherein the second test condition comprises:
applying a second stress condition to each of the plurality of DUTs, wherein the second stress condition is configured to apply the stress voltage to each of the plurality of DUTs;
applying a second measurement condition to a given DUT of the plurality of DUTs while maintaining the first stress condition at each of the remaining DUTs of the plurality of DUTs;
measuring a gate current at the given DUT; and
repeating the applying of the second stress condition and the second measurement condition for each DUT in the plurality of DUTs, wherein the first and second stress conditions are configured to shunt leakage current for each of the remaining DUTs of the plurality of DUTs current to a sink.

14. The method of claim 13 , wherein the applying of the second test further comprises:
determining that a particular DUT of the plurality of DUTs has a gate current greater than a threshold level; and
applying a disconnect condition to the particular DUT.

15. The method of claim 13 , further comprising determining expected degradation parameters characteristics for a DUT fabricated in a manner similar to each of the plurality of DUTs, wherein expected degradation parameters comprises at least two bias temperature instability (BTI), random telegraph noise (RTN), process variations and time dependent dielectric breakdown (TDDB).

16. The method of claim 13 , wherein the expected degradation parameters are based on a statistical analysis of the measured drain current and the measured gate current in the first and second test conditions.

17. The method of claim 13 , wherein the applying of the first test condition further comprises:
applying a recovery condition to each of the plurality of DUTs, wherein the recovery condition is configured to apply voltage to each of the plurality of DUTs that is lower than a rated voltage of each of the plurality of DUTs;
applying the first measurement condition to a given DUT of the plurality of DUTs while maintaining the recovery condition at each of the remaining DUTs of the plurality of DUTs;
measuring a drain current at the given DUT; and
repeating the applying of the recovery condition and the first measurement condition for each DUT in the plurality of DUTs.

Assignees

• Texas Instruments Inc

Inventors

• Chen Min
• Reddy Vijay Kumar

Classifications

• G01R29/26

  Measuring noise figure; Measuring signal-to-noise ratio · CPC title

• G01R31/2855 Primary

  Environmental, reliability or burn-in testing · CPC title

• G01R31/2868

  Complete testing stations; systems; procedures; software aspects · CPC title

• G01R31/2623

  for measuring break-down voltage therefor · CPC title

• G01R31/2621 Primary

  for testing field effect transistors, i.e. FET's · CPC title