Test method and system for cut-in voltage

Patent metadata

Field	Value
Publication number	US-9696371-B2
Application number	US-201314759370-A
Country	US
Kind code	B2
Filing date	Dec 31, 2013
Priority date	Jan 23, 2013
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A test method and system for cut-in voltage. The method comprises: coarse scanning of the cut-in voltage: a grid voltage, i.e., the cut-in voltage, is quickly determined when a drain terminal current is greater than a target current for the first time ( 100 ); accurate scanning of the cut-in voltage: a scanning step length is shortened continuously until the scanning step length is shorter than a preset step length, and each time the scanning step length is shortened, the scanning is conducted according to the current shortened scanning step length on the basis of the cut-in voltage determined in the former time, and then the cut-in voltage under the condition of the current shortened scanning step length is determined again ( 200 ). The scanning voltage is automatically increased or decreased by the test method and system through adding high resolution and high precision test conversion into a second scanning test, and therefore the testing of the cut-in voltage becomes more efficient and more accurate.

First claim

What is claimed is:

1. A method for testing a cut-in voltage of a semiconductor performed by a testing system, comprising:
step A, coarsely scanning the cut-in voltage, including:
scanning voltage and current of a semiconductor at a coarse scanning step length of voltage and
determining a scanning cut-in voltage at the coarse scanning step length of voltage; and

step B, accurately scanning the cut-in voltage, including:
on a basis of the scanning cut-in voltage at the coarse scanning step length of voltage, scanning the voltage and the current of the semiconductor at a shortened scanning step length of voltage than a previous scanning step length of voltage,
determining a scanning cut-in voltage at the shortened scanning step length of voltage,
shortening further the shortened scanning step length of voltage continuously and scanning the voltage and the current of the semiconductor at the further shortened scanning step length of voltage until the scanning step length of voltage before a last scanning step length of voltage is less than a preset step length of voltage, and
calculating a cut-in voltage at the last scanning step length of voltage,

wherein the scanning cut-in voltage is a minimum gate electrode voltage which allows a drain electrode current to be greater than a target current at each scanning step length of voltage.

2. The method according to claim 1 , wherein step B comprises:
step B01, determining whether the previous scanning step length of voltage is greater than the preset step length of voltage, if the previous scanning step length of voltage is greater than or equal to the preset step length of voltage, then shortening the previous scanning step length of voltage to obtain a current scanning step length and executing step B02, and if the previous scanning step length of voltage is less than the preset step length of voltage, then executing step B05;
step B02, measuring a drain electrode current when a drain electrode voltage is the scanning cut-in voltage at the previous scanning step length of voltage, comparing the drain electrode current to the target current, if the drain electrode current is less than the target current, executing step B03, and if the drain electrode current is not less than the target current, executing step B04;
step B03, increasing the gate electrode voltage step by step according to the current scanning step length of voltage and measuring the corresponding drain electrode current until the drain electrode current is greater than or equal to the target current for the first time, then returning, as a scanning cut-in voltage at the current scanning step length of voltage, the gate electrode voltage when the drain electrode current is greater than or equal to the target current for the first time, simultaneously returning a drain electrode current corresponding to the scanning cut-in voltage at the current scanning step length of voltage, a maximum drain electrode current which is less than the target current in the scanning, and the corresponding gate electrode voltage, and executing the step B01 again;
step B04, decreasing the gate electrode voltage step by step according to the current scanning step length of voltage and measuring the corresponding drain electrode current until the drain electrode current is less than the target current for the first time, then returning the gate electrode voltage corresponding to a minimum drain electrode current which is greater than or equal to the target current, taking the gate electrode voltage corresponding to the minimum drain electrode current as the scanning cut-in voltage at the current scanning step length of voltage, simultaneously returning the drain electrode current corresponding to the scanning cut-in voltage at the current scanning step length of voltage, the maximum drain electrode current which is less than the target current in the step B04, and the corresponding gate electrode voltage, and executing the step B01 again; and
step B05, calculating a cut-in voltage returned by a last scanning result, the corresponding drain current, a maximum drain electrode current which is less than the target current at the last scanning step length of voltage, and the corresponding gate electrode voltage.

3. The method according to claim 2 , wherein, in the step B01, the shortening of the previous scanning step length of voltage comprises multiplying the previous scanning step length of voltage by a shortening coefficient λ, the shortening coefficient λ being subject to a range of 0<λ<1.

4. The method according to claim 3 , wherein the shortening coefficient λ, is 1/10.

5. The method according to claim 2 , wherein the step B04 further comprises: after each decrease of the gate electrode voltage, comparing the decreased gate electrode voltage to a voltage lower limit, if the decreased-gate electrode voltage is less than the voltage lower limit, returning an error.

6. The method according to claim 5 , wherein the voltage lower limit is set to be two times of an initial scanning gate electrode voltage.

7. The method according to claim 2 , wherein the step B03 further comprises: after each increase of the gate electrode voltage, comparing the increased gate electrode voltage to a voltage upper limit, if the increased gate electrode voltage is greater than the voltage upper limit, returning an error.

8. The method according to claim 7 , wherein the voltage upper limit is set to be two times of the maximum gate electrode voltage at the step B03.

9. The method according to claim 2 , wherein the step B05 further comprising directly returning the scanning cut-in voltage returned by the last scanning result as the cut-in voltage, or calculating via the following formula:
K =( I d2 −I d1 )/ V gstep ,
B =( V g2 *I d1 −V g1 *I d2 )/ V gstep
the R slt =P*(I target −B)/K is returned as the cut-in voltage;
wherein when the semiconductor is a P-type field effect transistor, the value of P is −1, and when the semiconductor is a N-type field effect transistor, the value of P is 1, and
V g2 represents a scanning cut-in voltage obtained by the last scanning result, I d2 represents the drain electrode current corresponding to the V g2 , I d1 represents the maximum drain electrode current value which is less than the target current at the last scanning, V g1 represents the gate electrode voltage corresponding to I d1 , V gstep represents the scanning step length at the last scanning, and I target represents the target current.

10. A non-transitory computer readable storage medium including a computer program stored thereon, the computer program comprising instructions to execute a method for testing a cut-in voltage of a semiconductor which is performed by a testing system, the method comprising:
step A, coarsely scanning the cut-in voltage, including:
scanning a voltage and current of a semiconductor at a coarse scanning step length of voltage and determining a scanning cut-in voltage at the coarse scanning step length of voltage; and
step B, accurately scanning the cut-in voltage, including:
on a basis of the scanning cut-in voltage at the coarse scanning step length of voltage, scanning the voltage and current of the semiconductor at a shortened scanning step length of voltage than a previous scanning step length of voltage, determining a scanning cut-in voltage at the shortened scanning step length of voltage,
shortening further the shortened scanning step length of voltage continuously and scanning the voltage and current of the semiconductor at the further shortened scanning step length of voltage until the scanning step length of voltage before a last scanning step length of voltage is les

Assignees

• Csmc Technologies Fab2 Co Ltd

Inventors

• Wang Ming
• Lian Xiaoqian
• Lin Yaojun
• Xu Wenhui
• Chen Hanshun

Classifications

• G01R31/2623 Primary

  for measuring break-down voltage therefor · CPC title

• G01R31/2621 Primary

  for testing field effect transistors, i.e. FET's · CPC title