Methods, apparatus and system for screening process splits for technology development

Patent metadata

Field	Value
Publication number	US-9702926-B2
Application number	US-201414288278-A
Country	US
Kind code	B2
Filing date	May 27, 2014
Priority date	May 27, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.

First claim

What is claimed:

1. A method, comprising:
providing a device having at least one transistor and at least one dielectric layer;
providing a test signal for performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on said device;
performing said TDDB test and said BTI test on said device based upon said test signal; and
performing at least one of acquiring, storing, or transmitting data relating to a breakdown of said dielectric layer and at least one characteristic of said transistor based upon said TDDB test and said BTI test.

2. The method of claim 1 , wherein providing said test signal comprises providing a voltage ramp signal comprising a first voltage level during a first stress time period, a second voltage level during a BTI sense time period, a third voltage level during a TDDB sense time period, and a fourth voltage level during a second stress time period, wherein said fourth voltage level is higher than said first voltage level by a ramp-step value.

3. The method of claim 2 , wherein performing said TDDB test and said BTI test comprises performing a TDDB sensing function during said TDDB sense time period, and a BTI sensing function during said BTI sense time period.

4. The method of claim 2 , wherein said second voltage level during said BTI sense time period is a gate threshold voltage level of said transistor, and wherein said third voltage level during said TDDB sense time period is at least one of a supply voltage level or an intended-use voltage level.

5. The method of claim 1 , wherein performing said TDDB test and said BTI test substantially simultaneously comprises determining at least one of a linear drain current, a saturation drain current, a linear gate threshold voltage, or a saturation gate threshold voltage of said transistor.

6. The method of claim 5 , wherein determining said saturation gate threshold voltage comprises determining a gate threshold voltage based upon said saturation drain current and an impedance of a portion of said transistor, and wherein determining said linear gate threshold voltage comprises determining said linear gate threshold voltage based upon said linear drain current and said impedance of said portion of said transistor.

7. The method of claim 6 , wherein said impedance is based upon a geometry of said portion of said transistor.

8. The method of claim 1 , wherein said device is comprised of at least one of said transistor, a capacitor, a resistor, memory cell, a CMOS device, a BiCMOS device, a Flash device, a DRAM memory device, and a power device.

9. The method of claim 1 , wherein said device is said transistor and said dielectric layer is a gate insulation layer for said transistor.

10. The method of claim 1 , wherein said dielectric layer is an inter-level or intra-level dielectric layer of a semiconductor device.

11. The method of claim 1 , wherein performing said TDDB test and said BTI test comprises performing said TDDB test and said BTI test at a predetermined temperature.

12. The method of claim 1 , further comprising modifying at least one process parameter based upon said TDDB test and said BTI test comprises modifying at least one of a temperature, a pressure, a duration, a process gas composition, a process gas concentration, and an applied voltage of a process operation.

13. A system, comprising:
a semiconductor device processing system to provide a device comprising at least one transistor and at least one dielectric layer;
a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system; and
a testing module for providing a voltage ramp signal (VRS) test signal for performing a bias temperature instability (BTI) and a time-dependent dielectric breakdown (TDDB) test on said device and provide data relating to a breakdown of said dielectric layer and at least one characteristic of said transistor based upon said BTI test and said TDDB test.

14. The system of claim 13 , wherein said processing controller is configured to modify at least one process parameter based upon said data relating to the breakdown of said dielectric layer and at least one characteristic of said transistor.

15. The system of claim 13 , further comprising:
a testing controller operatively coupled to said testing module, said testing controller configured to control an operation of said testing module; and
a test data analysis unit to perform an analysis of said data relating to the breakdown of said dielectric layer and at least one characteristic of said transistor, said test data analysis unit to provide analysis data to said processing controller for modifying at least one process parameter.

16. The system of claim 13 , wherein said VRS test signal comprises a plurality of pulse cycles, wherein each pulse cycle comprises a stress time period and a sense time period, wherein said stress time period comprises a pulse that progressively rises in each subsequent cycle and wherein said sense time period comprises a TDDB sense period and a BTI sense period.

17. The system of claim 16 , wherein the value of the VRS test signal during said TDDB sense period is at least one of a supply voltage level or an intended-use voltage level, and wherein said value of said VRS test signal during said BTI sense period is a gate threshold voltage level of said transistor.

18. The system of claim 16 , wherein said testing module comprises:
a pulse generator for generating said VRS test signal;
a measurement tool to measure at least one of a linear drain current, a saturation drain current, a gate threshold voltage, or a linear gate threshold voltage of said transistor;
a switch to change from said stress mode to said sensor mode; and
a controller to control an operation of at least one of said pulse generator, said measurement tool, and said switch.

19. A method, comprising:
receiving a first device having at least one transistor and a dielectric layer for testing;
providing a test signal for performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test onto the gate of said transistor, wherein said test signal comprises a plurality of pulse cycles, wherein each pulse cycle comprises a stress time period and a sense time period, wherein said stress time period comprises a pulse that progressively rises in each subsequent cycle and wherein said sense time period comprises a TDDB sense period and a BTI sense period;
performing said TDDB test and said BTI test on said device by performing sensing functions during said TDDB and BTI sense periods for providing data relating to a breakdown of said dielectric layer and at least one characteristic of said transistor based upon said TDDB test and said BTI test; and
modifying at least one process parameter based upon said data.

20. The method of claim 19 , wherein performing said TDDB test and said BTI test comprises determining at least one of a linear drain current, a saturation drain current, a saturation gate threshold voltage, or a linear gate threshold voltage of said transistor.

Assignees

• Globalfoundries Inc

Inventors

• Uppal Suresh
• Kerber Andreas
• Mcmahon William

Classifications

• G01R31/2874

  related to temperature · CPC title

• G01R31/2642 Primary

  Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests · CPC title

• G01R31/2607

  Circuits therefor (G01R31/2642 takes precedence) · CPC title

• G01R31/129 Primary

  of components or parts made of semiconducting materials; of LV components or parts (G01R31/18 takes precedence) · CPC title

• G01R31/2623

  for measuring break-down voltage therefor · CPC title