Contact over active gate structures for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-2021234022-A1
Application number	US-202117227165-A
Country	US
Kind code	A1
Filing date	Apr 9, 2021
Priority date	Nov 30, 2017
Publication date	Jul 29, 2021
Grant date	—

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a fin comprising silicon, the fin having a top and sidewalls; a gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin; a gate electrode over the gate dielectric layer, over the top of the fin and laterally adjacent the sidewalls of the fin, the gate electrode having a first side and a second side opposite the first side, a gate insulating cap on the gate electrode, the gate insulating cap having a top surface and a bottom surface; a dielectric spacer adjacent the first side of the gate electrode and adjacent the gate insulating cap; a semiconductor source or drain region adjacent the dielectric spacer; a trench contact structure over the semiconductor source or drain region, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the top surface of the gate insulating cap, and the insulating cap of the trench contact structure having a bottom surface above the bottom surface of the gate insulating cap.

2 . The integrated circuit structure of claim 1 , further comprising:
a conductive via on and electrically connected to a portion of the gate electrode over the top of the fin, the conductive via in an opening in the gate insulating cap.

3 . The integrated circuit structure of claim 2 , wherein the conductive via is on a portion of the insulating cap of the trench contact structure but is not electrically connected to the conductive structure of the trench contact structure.

4 . The integrated circuit structure of claim 3 , wherein the conductive via is in an eroded portion of the insulating cap of the trench contact structure.

5 . The integrated circuit structure of claim 2 , further comprising:
a second conductive via on and electrically connected to a portion of the trench contact structure, the second conductive via in an opening of the insulating cap of the trench contact structure.

6 . The integrated circuit structure of claim 5 , wherein the second conductive via is on a portion of the gate insulating cap but is not electrically connected to the gate electrode.

7 . The integrated circuit structure of claim 6 , wherein the second conductive via is in an eroded portion of the gate insulating cap.

8 . The integrated circuit structure of claim 5 , wherein the second conductive via is isolated from the conductive via.

9 . The integrated circuit structure of claim 5 , wherein the second conductive via is merged with the conductive via.

10 . The integrated circuit structure of claim 1 , further comprising:
a conductive via on and electrically connected to a portion of the trench contact structure, the conductive via in an opening of the insulating cap of the trench contact structure.

11 . The integrated circuit structure of claim 10 , wherein the conductive via is on a portion of the gate insulating cap but is not electrically connected to the gate electrode.

12 . The integrated circuit structure of claim 11 , wherein the conductive via is in an eroded portion of the gate insulating cap.

13 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure comprising:
a fin comprising silicon, the fin having a top and sidewalls;
a gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin;
a gate electrode over the gate dielectric layer, over the top of the fin and laterally adjacent the sidewalls of the fin, the gate electrode having a first side and a second side opposite the first side,
a gate insulating cap on the gate electrode, the gate insulating cap having a top surface and a bottom surface;
a dielectric spacer adjacent the first side of the gate electrode and adjacent the gate insulating cap;
a semiconductor source or drain region adjacent the dielectric spacer;
a trench contact structure over the semiconductor source or drain region, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the top surface of the gate insulating cap, and the insulating cap of the trench contact structure having a bottom surface above the bottom surface of the gate insulating cap.

14 . The computing device of claim 13 , further comprising:
a memory coupled to the board.

15 . The computing device of claim 13 , further comprising:
a communication chip coupled to the board.

16 . The computing device of claim 13 , further comprising:
a camera coupled to the board.

17 . The computing device of claim 13 , further comprising:
a battery coupled to the board.

18 . The computing device of claim 13 , further comprising:
an antenna coupled to the board.

19 . The computing device of claim 13 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

20 . The computing device of claim 13 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.

Assignees

• Intel Corp

Inventors

• Yeoh Andrew W
• Ghani Tahir
• Madhavan Atul
• Hattendorf Michael L
• Auth Christopher P

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title