Contact over active gate structures for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-10541316-B2
Application number	US-201715859412-A
Country	US
Kind code	B2
Filing date	Dec 30, 2017
Priority date	Nov 30, 2017
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a fin comprising silicon, the fin having a top and sidewalls;
first and second gate dielectric layers over the top of the fin and laterally adjacent the sidewalls of the fin;
first and second gate electrodes over the first and second gate dielectric layers, respectively, over the top of the fin and laterally adjacent the sidewalls of the fin, the first and second gate electrodes both having a first side and a second side opposite the first side, and both having an insulating cap having a top surface;
a first dielectric spacer adjacent the first side of the first gate electrode;
a second dielectric spacer adjacent the second side of the second gate electrode;
a semiconductor source or drain region adjacent the first and second dielectric spacers;
a trench contact structure over the semiconductor source or drain region adjacent the first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes, and the insulating cap of the trench contact structure extending laterally into recesses in the first and second dielectric spacers and overhanging the conductive structure of the trench contact structure.

2. The integrated circuit structure of claim 1 , further comprising:
a conductive via on and electrically connected to a portion of the first gate electrode over the top of the fin, the conductive via in an opening in the insulating cap of the first gate electrode.

3. The integrated circuit structure of claim 2 , wherein the conductive via is on a portion of the insulating cap of the trench contact structure but is not electrically connected to the conductive structure of the trench contact structure.

4. The integrated circuit structure of claim 3 , wherein the conductive via is in an eroded portion of the insulating cap of the trench contact structure.

5. The integrated circuit structure of claim 2 , further comprising:
a second conductive via on and electrically connected to a portion of the trench contact structure, the second conductive via in an opening of the insulating cap of the trench contact structure.

6. The integrated circuit structure of claim 5 , wherein the second conductive via is on a portion of the insulating caps of the first and second gate electrodes but is not electrically connected to the first and second gate electrodes.

7. The integrated circuit structure of claim 6 , wherein the second conductive via is in an eroded portion of the insulating caps of the first and second gate electrodes.

8. The integrated circuit structure of claim 5 , wherein the second conductive via is isolated from the conductive via.

9. The integrated circuit structure of claim 5 , wherein the second conductive via is merged with the conductive via.

10. The integrated circuit structure of claim 1 , further comprising:
a conductive via on and electrically connected to a portion of the trench contact structure, the conductive via in an opening of the insulating cap of the trench contact structure.

11. The integrated circuit structure of claim 10 , wherein the conductive via is on a portion of the insulating caps of the first and second gate electrodes but is not electrically connected to the first and second gate electrodes.

12. The integrated circuit structure of claim 11 , wherein the conductive via is in an eroded portion of one or both of the insulating caps of the first and second gate electrodes.

13. The integrated circuit structure of claim 1 , wherein the insulating cap of the trench contact structure has a composition different than a composition of the insulating caps of the first and second gate electrodes.

14. The integrated circuit structure of claim 1 , wherein the insulating caps of the first and second gate electrodes both have a bottom surface substantially co-planar with a bottom surface of the insulating cap of the trench contact structure.

15. The integrated circuit structure of claim 1 , wherein the insulating caps of the first and second gate electrodes both have a bottom surface below a bottom surface of the insulating cap of the trench contact structure.

16. The integrated circuit structure of claim 1 , wherein the insulating caps of the first and second gate electrodes both have a bottom surface above a bottom surface of the insulating cap of the trench contact structure.

17. The integrated circuit structure of claim 1 , wherein the conductive structure of the trench contact structure comprises a U-shaped metal layer, a T-shaped metal layer on and over the entirety of the U-shaped metal layer, and a third metal layer on the T-shaped metal layer, wherein the insulating cap of the trench contact structure is on the third metal layer.

18. The integrated circuit structure of claim 17 , wherein the third metal layer and the U-shaped metal layer comprise titanium, and wherein the T-shaped metal layer comprises cobalt.

19. The integrated circuit structure of claim 18 , wherein the T-shaped metal layer further comprises carbon.

20. The integrated circuit structure of claim 1 , further comprising:
a metal silicide layer directly between the conductive structure of the trench contact structure and the semiconductor source or drain region.

21. The integrated circuit structure of claim 20 , wherein the metal silicide layer comprises titanium and silicon.

22. The integrated circuit structure of claim 21 , wherein the semiconductor source or drain region is an N-type semiconductor source or drain region.

23. The integrated circuit structure of claim 20 , wherein the metal silicide layer comprises nickel, platinum and silicon.

24. The integrated circuit structure of claim 23 , wherein the semiconductor source or drain region is a P-type semiconductor source or drain region.

25. The integrated circuit structure of claim 23 , wherein the metal silicide layer further comprises germanium.

Assignees

• Intel Corp

Inventors

• Yeoh Andrew W
• Ghani Tahir
• Madhavan Atul
• Hattendorf Michael L
• Auth Christopher P

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title